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Prepare for SP-addressed locals

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* libguile/vm-engine.c: Renumber opcodes, and take the opportunity to
  fold recent additions into more logical places.  Be more precise when
  describing the encoding of operands, to shuffle local references only
  and not constants, immediates, or other such values.
  (SP_REF, SP_SET): New helpers.
  (BR_BINARY, BR_ARITHMETIC): Take full 24-bit operands.  Our shuffle
  strategy is to emit push when needed to bring far locals near, then
  pop afterwards, shuffling away far destination values as needed; but
  that doesn't work for conditionals, unless we introduce a trampoline.
  Let's just do the simple thing for now.  Native compilation will use
  condition codes.
  (push, pop, drop): Back from the dead!  We'll only use these for
  temporary shuffling though, when an opcode can't address the full
  24-bit range.
  (long-fmov): New instruction, like long-mov but relative to the frame
  pointer.
  (load-typed-array, make-array): Don't use a compressed encoding so
  that we can avoid the shuffling case.  It would be a pain, given that
  they have so many operands already.

* module/language/bytecode.scm (compute-instruction-arity): Update for
  new instrution word encodings.

* module/system/vm/assembler.scm: Update to expose some opcodes
  directly, without the need for shuffling wrappers.  Adapt to
  instruction word encodings change.

* module/system/vm/disassembler.scm (disassembler): Adapt to instruction
  coding change.
This commit is contained in:
Andy Wingo 2015-10-20 20:06:40 +02:00
parent 72353de77d
commit 0da0308b84
5 changed files with 494 additions and 386 deletions
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52
libguile/instructions.c
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@ -31,30 +31,34 @@ SCM_SYMBOL (sym_left_arrow, "<-");
SCM_SYMBOL (sym_bang, "!");
#define OP_HAS_ARITY (1U << 0)
#define FOR_EACH_INSTRUCTION_WORD_TYPE(M) \
M(X32) \
M(U8_X24) \
M(U8_U24) \
M(U8_L24) \
M(U8_U8_I16) \
M(U8_U8_U8_U8) \
M(U8_U12_U12) \
M(U32) /* Unsigned. */ \
M(X8_S24) \
M(X8_F24) \
M(X8_L24) \
M(X8_C24) \
M(X8_S8_I16) \
M(X8_S12_S12) \
M(X8_S12_C12) \
M(X8_C12_C12) \
M(X8_F12_F12) \
M(X8_S8_S8_S8) \
M(X8_S8_C8_S8) \
M(X8_S8_S8_C8) \
M(C8_C24) \
M(C32) /* Unsigned. */ \
M(I32) /* Immediate. */ \
M(A32) /* Immediate, high bits. */ \
M(B32) /* Immediate, low bits. */ \
M(N32) /* Non-immediate. */ \
M(S32) /* Scheme value (indirected). */ \
M(R32) /* Scheme value (indirected). */ \
M(L32) /* Label. */ \
M(LO32) /* Label with offset. */ \
M(X8_U24) \
M(X8_U12_U12) \
M(X8_L24) \
M(B1_C7_L24) \
M(B1_X7_L24) \
M(B1_U7_L24) \
M(B1_X7_U24) \
M(B1_X7_C24) \
M(B1_X7_S24) \
M(B1_X7_F24) \
M(B1_X31)
#define TYPE_WIDTH 5
@ -73,7 +77,7 @@ static SCM word_type_symbols[] =
#undef FALSE
};
#define OP(n,type) ((type) << (n*TYPE_WIDTH))
#define OP(n,type) (((type) + 1) << (n*TYPE_WIDTH))
/* The VM_DEFINE_OP macro uses a CPP-based DSL to describe what kinds of
arguments each instruction takes. This piece of code is the only
@ -99,8 +103,12 @@ static SCM word_type_symbols[] =
#define OP_DST (1 << (TYPE_WIDTH * 5))
#define WORD_TYPE(n, word) \
#define WORD_TYPE_AND_FLAG(n, word) \
(((word) >> ((n) * TYPE_WIDTH)) & ((1 << TYPE_WIDTH) - 1))
#define WORD_TYPE(n, word) \
(WORD_TYPE_AND_FLAG (n, word) - 1)
#define HAS_WORD(n, word) \
(WORD_TYPE_AND_FLAG (n, word) != 0)
/* Scheme interface */
@ -112,15 +120,15 @@ parse_instruction (scm_t_uint8 opcode, const char *name, scm_t_uint32 meta)
/* Format: (name opcode word0 word1 ...) */
if (WORD_TYPE (4, meta))
if (HAS_WORD (4, meta))
len = 5;
else if (WORD_TYPE (3, meta))
else if (HAS_WORD (3, meta))
len = 4;
else if (WORD_TYPE (2, meta))
else if (HAS_WORD (2, meta))
len = 3;
else if (WORD_TYPE (1, meta))
else if (HAS_WORD (1, meta))
len = 2;
else if (WORD_TYPE (0, meta))
else if (HAS_WORD (0, meta))
len = 1;
else
abort ();