mirror/guile
mirror/guile
1
Fork 0
mirror of https://git.savannah.gnu.org/git/guile.git synced 2025-06-04 03:00:20 +02:00
Code Activity

X86: %r12 may be used as an index register.

Browse source 
* lib/jit_x86-cpu.c: Correct not properly tested case of using
	%r12 as index register, what was causing an invalid assertion.
	%r12 is mapped to the "extra" JIT_R3 register, and test cases
	only test "standard" lightning registers.
This commit is contained in:
pcpa 2013-09-30 13:30:21 -03:00
parent ff73547603
commit 1bd169cfa3
2 changed files with 9 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

7
ChangeLog
View file

@ -1,3 +1,10 @@
2013-10-30 Paulo Andrade <pcpa@gnu.org>
* lib/jit_x86-cpu.c: Correct not properly tested case of using
%r12 as index register, what was causing an invalid assertion.
%r12 is mapped to the "extra" JIT_R3 register, and test cases
only test "standard" lightning registers.
2013-10-28 Paulo Andrade <pcpa@gnu.org>
* lib/jit_ia64.c: Minor change to force collecting the maximum

3
lib/jit_x86-cpu.c
View file

@ -61,6 +61,7 @@
# define _R14_REGNO 14
# define _R15_REGNO 15
# define r7(reg) (reg & 7)
# define r8(reg) (reg & 15)
# define _SCL1 0x00
# define _SCL2 0x01
# define _SCL4 0x02
@ -701,7 +702,7 @@ _rx(jit_state_t *_jit, jit_int32_t rd, jit_int32_t md,
sib(ms, r7(ri), 0x05);
ii(md);
}
else if (r7(ri) != _RSP_REGNO) {
else if (r8(ri) != _RSP_REGNO) {
if (md == 0 && r7(rb) != _RBP_REGNO) {
mrm(0x00, r7(rd), 0x04);
sib(ms, r7(ri), r7(rb));