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refine ludovic's doc patch

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git-archimport-id: bonzini@gnu.org--2004b/lightning--stable--1.2--patch-51
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Paolo Bonzini 2006-11-23 09:06:07 +00:00
parent 67d0c9a3f1
commit 36a3ae9058
1 changed files with 12 additions and 8 deletions
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doc/using.texi
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@ -100,20 +100,24 @@ preserved across function calls (@code{V0}, @code{V1} and
@code{R2}). Six registers are not very much, but this @code{R2}). Six registers are not very much, but this
restriction was forced by the need to target CISC architectures restriction was forced by the need to target CISC architectures
which, like the x86, are poor of registers; anyway, backends can which, like the x86, are poor of registers; anyway, backends can
specify the actual number of available caller- and callee-save specify the actual number of available registers with the macros
registers with the macros @code{JIT_R_NUM} and @code{JIT_V_NUM}. @code{JIT_R_NUM} (for caller-save registers) and @code{JIT_V_NUM}
(for callee-save registers).
In addition, there is a special @code{RET} register which contains the In addition, there is a special @code{RET} register which contains
return value of the current function (@emph{not} the return value of the return value of the current function (@emph{not} the return value
callees---use the @code{retval} instruction for this). You should of callees---use the @code{retval} instruction for this). You should
always remember, however, that writing this register could overwrite always remember, however, that writing this register could overwrite
either a general-purpose register or an incoming parameter, depending either a general-purpose register or an incoming parameter, depending
on the architecture. on the architecture.
There are at least six floating-point registers, named @code{FPR0} to There are at least six floating-point registers, named @code{FPR0} to
@code{FPR5}. These are separate from the integer registers on @code{FPR5}. These are caller-save and are separate from the integer
all the supported architectures; on Intel architectures, the registers on all the supported architectures; on Intel architectures,
register stack is mapped to a flat register file. the register stack is mapped to a flat register file. As for the
integer registers, the macro @code{JIT_FPR_NUM} yields the number of
floating-point registers, and the special @code{FPRET} register contains
the return value of the current function.
The complete instruction set follows; as you can see, most non-memory The complete instruction set follows; as you can see, most non-memory
operations only take integers, long integers (either signed or operations only take integers, long integers (either signed or