From 72f3e65a6d6ffeeadfb9ba3d5b8980ac2b878a90 Mon Sep 17 00:00:00 2001 From: pcpa Date: Tue, 8 Oct 2013 01:20:19 -0300 Subject: [PATCH] ARM: Correct wrong offset for load/store of floats. * lib/jit_arm-vfp.c: Correct wrong load/store offset calculation when the displacement is constant but too large to use an instruction with an immediate offset. --- ChangeLog | 6 ++++++ lib/jit_arm-vfp.c | 40 ++++++++++++++++------------------------ 2 files changed, 22 insertions(+), 24 deletions(-) diff --git a/ChangeLog b/ChangeLog index c81dd8802..1fe7608c7 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,9 @@ +2013-10-08 Paulo Andrade + + * lib/jit_arm-vfp.c: Correct wrong load/store offset + calculation when the displacement is constant but too + large to use an instruction with an immediate offset. + 2013-10-07 Paulo Andrade * check/self.c: Extend tests to validate jit_callee_save_p diff --git a/lib/jit_arm-vfp.c b/lib/jit_arm-vfp.c index e1e8dfb42..c1ee41e77 100644 --- a/lib/jit_arm-vfp.c +++ b/lib/jit_arm-vfp.c @@ -2096,9 +2096,8 @@ _vfp_ldxi_f(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0) if (jit_fpr_p(r0)) { if (i0 >= 0) { assert(!(i0 & 3)); - i0 >>= 2; - if (i0 < 256) - VLDR_F32(r0, r1, i0); + if (i0 < 1024) + VLDR_F32(r0, r1, i0 >> 2); else { reg = jit_get_reg(jit_class_gpr); addi(rn(reg), r1, i0); @@ -2109,9 +2108,8 @@ _vfp_ldxi_f(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0) else { i0 = -i0; assert(!(i0 & 3)); - i0 >>= 2; - if (i0 < 256) - VLDRN_F32(r0, r1, i0); + if (i0 < 1024) + VLDRN_F32(r0, r1, i0 >> 2); else { reg = jit_get_reg(jit_class_gpr); subi(rn(reg), r1, i0); @@ -2131,9 +2129,8 @@ _vfp_ldxi_d(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0) if (jit_fpr_p(r0)) { if (i0 >= 0) { assert(!(i0 & 3)); - i0 >>= 2; - if (i0 < 256) - VLDR_F64(r0, r1, i0); + if (i0 < 1024) + VLDR_F64(r0, r1, i0 >> 2); else { reg = jit_get_reg(jit_class_gpr); addi(rn(reg), r1, i0); @@ -2144,9 +2141,8 @@ _vfp_ldxi_d(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0) else { i0 = -i0; assert(!(i0 & 3)); - i0 >>= 2; - if (i0 < 256) - VLDRN_F64(r0, r1, i0); + if (i0 < 1024) + VLDRN_F64(r0, r1, i0 >> 2); else { reg = jit_get_reg(jit_class_gpr); subi(rn(reg), r1, i0); @@ -2229,9 +2225,8 @@ _vfp_stxi_f(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1) if (jit_fpr_p(r1)) { if (i0 >= 0) { assert(!(i0 & 3)); - i0 >>= 2; - if (i0 < 256) - VSTR_F32(r1, r0, i0); + if (i0 < 1024) + VSTR_F32(r1, r0, i0 >> 2); else { reg = jit_get_reg(jit_class_gpr); addi(rn(reg), r0, i0); @@ -2242,9 +2237,8 @@ _vfp_stxi_f(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1) else { i0 = -i0; assert(!(i0 & 3)); - i0 >>= 2; - if (i0 < 256) - VSTRN_F32(r1, r0, i0); + if (i0 < 1024) + VSTRN_F32(r1, r0, i0 >> 2); else { reg = jit_get_reg(jit_class_gpr); subi(rn(reg), r0, i0); @@ -2264,9 +2258,8 @@ _vfp_stxi_d(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1) if (jit_fpr_p(r1)) { if (i0 >= 0) { assert(!(i0 & 3)); - i0 >>= 2; - if (i0 < 256) - VSTR_F64(r1, r0, i0); + if (i0 < 0124) + VSTR_F64(r1, r0, i0 >> 2); else { reg = jit_get_reg(jit_class_gpr); addi(rn(reg), r0, i0); @@ -2277,9 +2270,8 @@ _vfp_stxi_d(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1) else { i0 = -i0; assert(!(i0 & 3)); - i0 >>= 2; - if (i0 < 256) - VSTRN_F64(r1, r0, i0); + if (i0 < 1024) + VSTRN_F64(r1, r0, i0 >> 2); else { reg = jit_get_reg(jit_class_gpr); subi(rn(reg), r0, i0);