From 746660bf08ca99e2f25ad2715632e4c451832abe Mon Sep 17 00:00:00 2001
From: Ekaitz Zarraga <ekaitz@elenq.tech>
Date: Fri, 15 Nov 2024 12:01:52 +0100
Subject: [PATCH] riscv: movi: use addiw in RV64

---
 lightening/riscv-cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/lightening/riscv-cpu.c b/lightening/riscv-cpu.c
index bd2fff593..92ee7cf1f 100644
--- a/lightening/riscv-cpu.c
+++ b/lightening/riscv-cpu.c
@@ -1585,7 +1585,11 @@ movi(jit_state_t *_jit, int32_t r0, jit_word_t i0)
     }
 
     if(lo || hi == 0){
+#if __WORDSIZE == 64
+      em_wp(_jit, _ADDIW(r0, srcreg, lo));
+#elif __WORDSIZE == 32
       em_wp(_jit, _ADDI(r0, srcreg, lo));
+#endif
     }
 
   } else {