mirror of
https://git.savannah.gnu.org/git/guile.git
synced 2025-06-21 19:20:21 +02:00
Make it simpler to add support for more than 64 registers.
* include/lightning/jit_private.h, lib/jit_arm.c, lib/jit_mips-cpu.c, lib/jit_mips.c, lib/jit_ppc-cpu.c, lib/jit_ppc.c, lib/jit_print.c, lib/jit_sparc-cpu.c, lib/jit_sparc.c, lib/jit_x86-cpu.c, lib/jit_x86.c, lib/lightning.c: Change all jit_regset macros to take a pointer argument, to avoid structure copies when adding a port to an architecture with more than 64 registers.
This commit is contained in:
pcpa
parent
066db584c9
commit
7bdd22bd99
13 changed files with 310 additions and 309 deletions
281
lib/lightning.c
281
lib/lightning.c
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@ -182,19 +182,19 @@ _jit_get_reg(jit_state_t *_jit, jit_int32_t regspec)
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spec = regspec & ~(jit_class_chk|jit_class_nospill);
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if (spec & jit_class_named) {
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regno = jit_regno(spec);
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if (jit_regset_tstbit(_jitc->regsav, regno))
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if (jit_regset_tstbit(&_jitc->regsav, regno))
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/* fail if register is spilled */
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goto fail;
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if (jit_regset_tstbit(_jitc->regarg, regno))
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if (jit_regset_tstbit(&_jitc->regarg, regno))
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/* fail if register is an argument to current instruction */
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goto fail;
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if (jit_regset_tstbit(_jitc->reglive, regno)) {
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if (jit_regset_tstbit(&_jitc->reglive, regno)) {
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if (regspec & jit_class_nospill)
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/* fail if register is live and should not spill/reload */
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goto fail;
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goto spill;
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}
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jit_regset_setbit(_jitc->regarg, regno);
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jit_regset_setbit(&_jitc->regarg, regno);
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return (regno);
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}
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else
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@ -204,8 +204,8 @@ _jit_get_reg(jit_state_t *_jit, jit_int32_t regspec)
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/* search for a free register matching spec */
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for (regno = 0; regno < _jitc->reglen; regno++) {
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if ((jit_class(_rvs[regno].spec) & spec) == spec &&
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!jit_regset_tstbit(_jitc->regarg, regno) &&
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!jit_regset_tstbit(_jitc->reglive, regno))
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!jit_regset_tstbit(&_jitc->regarg, regno) &&
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!jit_regset_tstbit(&_jitc->reglive, regno))
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goto regarg;
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}
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@ -213,8 +213,8 @@ _jit_get_reg(jit_state_t *_jit, jit_int32_t regspec)
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* for the current instruction */
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for (regno = 0; regno < _jitc->reglen; regno++) {
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if ((jit_class(_rvs[regno].spec) & spec) == spec &&
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!jit_regset_tstbit(_jitc->regsav, regno) &&
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!jit_regset_tstbit(_jitc->regarg, regno) &&
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!jit_regset_tstbit(&_jitc->regsav, regno) &&
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!jit_regset_tstbit(&_jitc->regarg, regno) &&
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!(regspec & jit_class_nospill)) {
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spill:
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assert(_jitc->function);
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@ -234,15 +234,15 @@ _jit_get_reg(jit_state_t *_jit, jit_int32_t regspec)
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}
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emit_stxi_d(_jitc->function->regoff[regno], JIT_FP, regno);
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}
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jit_regset_setbit(_jitc->regsav, regno);
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jit_regset_setbit(&_jitc->regsav, regno);
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regarg:
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jit_regset_setbit(_jitc->regarg, regno);
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jit_regset_setbit(&_jitc->regarg, regno);
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if (jit_class(_rvs[regno].spec) & jit_class_sav) {
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/* if will modify callee save registers without a
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* function prolog, better patch this assertion */
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assert(_jitc->function);
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if (!jit_regset_tstbit(_jitc->function->regset, regno)) {
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jit_regset_setbit(_jitc->function->regset, regno);
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if (!jit_regset_tstbit(&_jitc->function->regset, regno)) {
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jit_regset_setbit(&_jitc->function->regset, regno);
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_jitc->again = 1;
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}
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}
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@ -255,10 +255,10 @@ _jit_get_reg(jit_state_t *_jit, jit_int32_t regspec)
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assert(!(regspec & jit_class_nospill));
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for (regno = 0; regno < _jitc->reglen; regno++) {
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if ((jit_class(_rvs[regno].spec) & spec) == spec &&
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!jit_regset_tstbit(_jitc->regsav, regno) &&
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!jit_regset_tstbit(_jitc->regarg, regno)) {
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jit_regset_setbit(_jitc->regarg, regno);
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jit_regset_setbit(_jitc->regsav, regno);
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!jit_regset_tstbit(&_jitc->regsav, regno) &&
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!jit_regset_tstbit(&_jitc->regarg, regno)) {
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jit_regset_setbit(&_jitc->regarg, regno);
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jit_regset_setbit(&_jitc->regsav, regno);
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jit_save(regno);
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return (jit_regno_patch|regno);
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}
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@ -275,7 +275,7 @@ void
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_jit_unget_reg(jit_state_t *_jit, jit_int32_t regno)
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{
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regno = jit_regno(regno);
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if (jit_regset_tstbit(_jitc->regsav, regno)) {
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if (jit_regset_tstbit(&_jitc->regsav, regno)) {
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if (_jitc->emit) {
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if (jit_class(_rvs[regno].spec) & jit_class_gpr)
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emit_ldxi(regno, JIT_FP, _jitc->function->regoff[regno]);
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@ -284,18 +284,18 @@ _jit_unget_reg(jit_state_t *_jit, jit_int32_t regno)
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}
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else
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jit_load(regno);
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jit_regset_clrbit(_jitc->regsav, regno);
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jit_regset_clrbit(&_jitc->regsav, regno);
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}
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assert(jit_regset_tstbit(_jitc->regarg, regno));
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jit_regset_clrbit(_jitc->regarg, regno);
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assert(jit_regset_tstbit(&_jitc->regarg, regno));
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jit_regset_clrbit(&_jitc->regarg, regno);
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}
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unsigned long
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jit_regset_scan1(jit_regset_t set, jit_int32_t offset)
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jit_regset_scan1(jit_regset_t *set, jit_int32_t offset)
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{
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assert(offset >= 0 && offset <= 63);
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for (; offset < 64; offset++) {
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if (set & (1LL << offset))
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if (*set & (1LL << offset))
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return (offset);
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}
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return (ULONG_MAX);
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@ -508,8 +508,8 @@ _del_label(jit_state_t *_jit, jit_node_t *prev, jit_node_t *node)
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/* del_label() should only be called when optimizing.
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* This will leave an empty block index */
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jit_regset_del(block->reglive);
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jit_regset_del(block->regmask);
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jit_regset_del(&block->reglive);
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jit_regset_del(&block->regmask);
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block->label = NULL;
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/* redundant, should be already true */
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@ -579,10 +579,10 @@ jit_new_state(void)
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jit_alloc((jit_pointer_t *)&_jit, sizeof(jit_state_t));
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jit_alloc((jit_pointer_t *)&_jitc, sizeof(jit_compiler_t));
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jit_regset_new(_jitc->regarg);
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jit_regset_new(_jitc->regsav);
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jit_regset_new(_jitc->reglive);
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jit_regset_new(_jitc->regmask);
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jit_regset_new(&_jitc->regarg);
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jit_regset_new(&_jitc->regsav);
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jit_regset_new(&_jitc->reglive);
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jit_regset_new(&_jitc->regmask);
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bmp_init();
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jit_init();
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@ -891,8 +891,8 @@ _jit_link(jit_state_t *_jit, jit_node_t *node)
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block = _jitc->blocks.ptr + _jitc->blocks.offset;
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block->label = node;
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node->v.w = _jitc->blocks.offset;
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jit_regset_new(block->reglive);
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jit_regset_new(block->regmask);
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jit_regset_new(&block->reglive);
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jit_regset_new(&block->regmask);
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++_jitc->blocks.offset;
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}
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@ -1216,7 +1216,7 @@ _jit_optimize(jit_state_t *_jit)
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if (!block->label)
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continue;
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if (block->label->code != jit_code_epilog) {
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jit_regset_set(_jitc->regmask, block->regmask);
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jit_regset_set(&_jitc->regmask, &block->regmask);
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jit_update(block->label->next, &block->reglive, &_jitc->regmask);
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}
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}
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@ -1283,11 +1283,11 @@ _jit_optimize(jit_state_t *_jit)
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if (_jitc->function) {
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if ((mask & (jit_cc_a0_reg|jit_cc_a0_chg)) ==
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(jit_cc_a0_reg|jit_cc_a0_chg))
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jit_regset_setbit(_jitc->function->regset,
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jit_regset_setbit(&_jitc->function->regset,
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jit_regno(node->u.w));
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if ((mask & (jit_cc_a1_reg|jit_cc_a1_chg)) ==
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(jit_cc_a1_reg|jit_cc_a1_chg))
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jit_regset_setbit(_jitc->function->regset,
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jit_regset_setbit(&_jitc->function->regset,
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jit_regno(node->v.w));
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}
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break;
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@ -1331,34 +1331,34 @@ _jit_reglive(jit_state_t *_jit, jit_node_t *node)
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switch (node->code) {
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case jit_code_label: case jit_code_prolog: case jit_code_epilog:
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block = _jitc->blocks.ptr + node->v.w;
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jit_regset_set(_jitc->reglive, block->reglive);
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jit_regset_set(&_jitc->reglive, &block->reglive);
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break;
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case jit_code_callr:
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value = jit_regno(node->u.w);
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if (!(node->u.w & jit_regno_patch)) {
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jit_regset_setbit(_jitc->reglive, value);
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jit_regset_setbit(&_jitc->reglive, value);
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}
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case jit_code_calli:
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for (value = 0; value < _jitc->reglen; value++) {
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spec = jit_class(_rvs[value].spec);
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if ((spec & jit_class_arg) && jit_regarg_p(node, value))
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jit_regset_setbit(_jitc->reglive, value);
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jit_regset_setbit(&_jitc->reglive, value);
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else if (!(spec & jit_class_sav))
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jit_regset_clrbit(_jitc->reglive, value);
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jit_regset_clrbit(&_jitc->reglive, value);
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}
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#if defined(JIT_RET)
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/* Explicitly set return registers as live, because retval
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* should be free to not create a note, and/or user not
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* call jit_retval (but not a good idea to expect JIT_R0
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* to match JIT_RET) */
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jit_regset_setbit(_jitc->reglive, JIT_RET);
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jit_regset_setbit(&_jitc->reglive, JIT_RET);
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# if __arm__
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/* FIXME need a better logic (and r2-r3 may contain results) */
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jit_regset_setbit(_jitc->reglive, _R1);
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jit_regset_setbit(&_jitc->reglive, _R1);
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# endif
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#endif
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#if defined(JIT_FRET)
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jit_regset_setbit(_jitc->reglive, JIT_FRET);
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jit_regset_setbit(&_jitc->reglive, JIT_FRET);
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#endif
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break;
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default:
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@ -1367,49 +1367,50 @@ _jit_reglive(jit_state_t *_jit, jit_node_t *node)
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if (value & jit_cc_a0_rlh) {
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if (!(node->u.q.l & jit_regno_patch)) {
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if (value & jit_cc_a0_chg) {
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jit_regset_clrbit(_jitc->reglive, node->u.q.l);
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jit_regset_setbit(_jitc->regmask, node->u.q.l);
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jit_regset_clrbit(&_jitc->reglive, node->u.q.l);
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jit_regset_setbit(&_jitc->regmask, node->u.q.l);
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}
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else
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jit_regset_setbit(_jitc->reglive, node->u.q.l);
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jit_regset_setbit(&_jitc->reglive, node->u.q.l);
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}
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if (!(node->u.q.h & jit_regno_patch)) {
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if (value & jit_cc_a0_chg) {
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jit_regset_clrbit(_jitc->reglive, node->u.q.h);
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jit_regset_setbit(_jitc->regmask, node->u.q.h);
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jit_regset_clrbit(&_jitc->reglive, node->u.q.h);
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jit_regset_setbit(&_jitc->regmask, node->u.q.h);
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}
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else
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jit_regset_setbit(_jitc->reglive, node->u.q.h);
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jit_regset_setbit(&_jitc->reglive, node->u.q.h);
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}
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}
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else {
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if (!(node->u.w & jit_regno_patch)) {
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if (value & jit_cc_a0_chg) {
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jit_regset_clrbit(_jitc->reglive, node->u.w);
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jit_regset_setbit(_jitc->regmask, node->u.w);
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jit_regset_clrbit(&_jitc->reglive, node->u.w);
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jit_regset_setbit(&_jitc->regmask, node->u.w);
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}
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else
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jit_regset_setbit(_jitc->reglive, node->u.w);
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jit_regset_setbit(&_jitc->reglive, node->u.w);
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}
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}
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}
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if ((value & jit_cc_a1_reg) && !(node->v.w & jit_regno_patch)) {
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if (value & jit_cc_a1_chg) {
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jit_regset_clrbit(_jitc->reglive, node->v.w);
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jit_regset_setbit(_jitc->regmask, node->v.w);
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jit_regset_clrbit(&_jitc->reglive, node->v.w);
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jit_regset_setbit(&_jitc->regmask, node->v.w);
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}
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else
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jit_regset_setbit(_jitc->reglive, node->v.w);
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jit_regset_setbit(&_jitc->reglive, node->v.w);
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}
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if ((value & jit_cc_a2_reg) && !(node->w.w & jit_regno_patch))
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jit_regset_setbit(_jitc->reglive, node->w.w);
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if (jit_regset_set_p(_jitc->regmask)) {
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jit_regset_setbit(&_jitc->reglive, node->w.w);
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if (jit_regset_set_p(&_jitc->regmask)) {
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bmp_zero();
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jit_update(node->next, &_jitc->reglive, &_jitc->regmask);
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if (jit_regset_set_p(_jitc->regmask)) {
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if (jit_regset_set_p(&_jitc->regmask)) {
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/* any unresolved live state is considered as live */
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jit_regset_ior(_jitc->reglive, _jitc->reglive, _jitc->regmask);
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jit_regset_set_ui(_jitc->regmask, 0);
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jit_regset_ior(&_jitc->reglive,
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&_jitc->reglive, &_jitc->regmask);
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jit_regset_set_ui(&_jitc->regmask, 0);
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}
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}
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break;
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@ -1421,16 +1422,16 @@ _jit_regarg_set(jit_state_t *_jit, jit_node_t *node, jit_int32_t value)
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{
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if (value & jit_cc_a0_reg) {
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if (value & jit_cc_a0_rlh) {
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jit_regset_setbit(_jitc->regarg, jit_regno(node->u.q.l));
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jit_regset_setbit(_jitc->regarg, jit_regno(node->u.q.h));
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jit_regset_setbit(&_jitc->regarg, jit_regno(node->u.q.l));
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jit_regset_setbit(&_jitc->regarg, jit_regno(node->u.q.h));
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}
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else
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jit_regset_setbit(_jitc->regarg, jit_regno(node->u.w));
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jit_regset_setbit(&_jitc->regarg, jit_regno(node->u.w));
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}
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if (value & jit_cc_a1_reg)
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jit_regset_setbit(_jitc->regarg, jit_regno(node->v.w));
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jit_regset_setbit(&_jitc->regarg, jit_regno(node->v.w));
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if (value & jit_cc_a2_reg)
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jit_regset_setbit(_jitc->regarg, jit_regno(node->w.w));
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jit_regset_setbit(&_jitc->regarg, jit_regno(node->w.w));
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}
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void
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@ -1438,16 +1439,16 @@ _jit_regarg_clr(jit_state_t *_jit, jit_node_t *node, jit_int32_t value)
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{
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if (value & jit_cc_a0_reg) {
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if (value & jit_cc_a0_rlh) {
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jit_regset_clrbit(_jitc->regarg, jit_regno(node->u.q.l));
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jit_regset_clrbit(_jitc->regarg, jit_regno(node->u.q.h));
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jit_regset_clrbit(&_jitc->regarg, jit_regno(node->u.q.l));
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jit_regset_clrbit(&_jitc->regarg, jit_regno(node->u.q.h));
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}
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else
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jit_regset_clrbit(_jitc->regarg, jit_regno(node->u.w));
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jit_regset_clrbit(&_jitc->regarg, jit_regno(node->u.w));
|
||||
}
|
||||
if (value & jit_cc_a1_reg)
|
||||
jit_regset_clrbit(_jitc->regarg, jit_regno(node->v.w));
|
||||
jit_regset_clrbit(&_jitc->regarg, jit_regno(node->v.w));
|
||||
if (value & jit_cc_a2_reg)
|
||||
jit_regset_clrbit(_jitc->regarg, jit_regno(node->w.w));
|
||||
jit_regset_clrbit(&_jitc->regarg, jit_regno(node->w.w));
|
||||
}
|
||||
|
||||
jit_pointer_t
|
||||
|
|
@ -1536,7 +1537,7 @@ _jit_setup(jit_state_t *_jit, jit_block_t *block)
|
|||
unsigned long value;
|
||||
|
||||
jump = 0;
|
||||
jit_regset_set_ui(regmask, (1LL << _jitc->reglen) - 1);
|
||||
jit_regset_set_mask(®mask, _jitc->reglen);
|
||||
for (node = block->label->next; node; node = node->next) {
|
||||
switch (node->code) {
|
||||
case jit_code_label: case jit_code_prolog:
|
||||
|
|
@ -1548,44 +1549,44 @@ _jit_setup(jit_state_t *_jit, jit_block_t *block)
|
|||
live = !(value & jit_cc_a0_chg);
|
||||
if (value & jit_cc_a0_rlh) {
|
||||
if (!(node->u.q.l & jit_regno_patch) &&
|
||||
jit_regset_tstbit(regmask, node->u.q.l)) {
|
||||
jit_regset_tstbit(®mask, node->u.q.l)) {
|
||||
if (live || !jump)
|
||||
jit_regset_clrbit(regmask, node->u.q.l);
|
||||
jit_regset_clrbit(®mask, node->u.q.l);
|
||||
if (live)
|
||||
jit_regset_setbit(reglive, node->u.q.l);
|
||||
jit_regset_setbit(®live, node->u.q.l);
|
||||
}
|
||||
if (!(node->u.q.h & jit_regno_patch) &&
|
||||
jit_regset_tstbit(regmask, node->u.q.h)) {
|
||||
jit_regset_tstbit(®mask, node->u.q.h)) {
|
||||
if (live || !jump)
|
||||
jit_regset_clrbit(regmask, node->u.q.h);
|
||||
jit_regset_clrbit(®mask, node->u.q.h);
|
||||
if (live)
|
||||
jit_regset_setbit(reglive, node->u.q.h);
|
||||
jit_regset_setbit(®live, node->u.q.h);
|
||||
}
|
||||
}
|
||||
else {
|
||||
if (!(node->u.w & jit_regno_patch) &&
|
||||
jit_regset_tstbit(regmask, node->u.w)) {
|
||||
jit_regset_tstbit(®mask, node->u.w)) {
|
||||
if (live || !jump)
|
||||
jit_regset_clrbit(regmask, node->u.w);
|
||||
jit_regset_clrbit(®mask, node->u.w);
|
||||
if (live)
|
||||
jit_regset_setbit(reglive, node->u.w);
|
||||
jit_regset_setbit(®live, node->u.w);
|
||||
}
|
||||
}
|
||||
}
|
||||
if ((value & jit_cc_a1_reg) &&
|
||||
!(node->v.w & jit_regno_patch) &&
|
||||
jit_regset_tstbit(regmask, node->v.w)) {
|
||||
jit_regset_tstbit(®mask, node->v.w)) {
|
||||
live = !(value & jit_cc_a1_chg);
|
||||
if (live || !jump)
|
||||
jit_regset_clrbit(regmask, node->v.w);
|
||||
jit_regset_clrbit(®mask, node->v.w);
|
||||
if (live)
|
||||
jit_regset_setbit(reglive, node->v.w);
|
||||
jit_regset_setbit(®live, node->v.w);
|
||||
}
|
||||
if ((value & jit_cc_a2_reg) &&
|
||||
!(node->w.w & jit_regno_patch) &&
|
||||
jit_regset_tstbit(regmask, node->w.w)) {
|
||||
jit_regset_clrbit(regmask, node->w.w);
|
||||
jit_regset_setbit(reglive, node->w.w);
|
||||
jit_regset_tstbit(®mask, node->w.w)) {
|
||||
jit_regset_clrbit(®mask, node->w.w);
|
||||
jit_regset_setbit(®live, node->w.w);
|
||||
}
|
||||
if (value & jit_cc_a0_jmp)
|
||||
jump = 1;
|
||||
|
|
@ -1615,7 +1616,7 @@ _jit_update(jit_state_t *_jit, jit_node_t *node,
|
|||
|
||||
for (; node; node = node->next) {
|
||||
restart:
|
||||
if (jit_regset_set_p(*mask) == 0)
|
||||
if (jit_regset_set_p(mask) == 0)
|
||||
break;
|
||||
switch (node->code) {
|
||||
case jit_code_label:
|
||||
|
|
@ -1623,96 +1624,96 @@ _jit_update(jit_state_t *_jit, jit_node_t *node,
|
|||
if (bmp_tst(node->v.w))
|
||||
return;
|
||||
bmp_set(node->v.w);
|
||||
jit_regset_and(ztmp, *mask, block->reglive);
|
||||
if (jit_regset_set_p(ztmp)) {
|
||||
jit_regset_ior(*live, *live, ztmp);
|
||||
jit_regset_com(ztmp, ztmp);
|
||||
jit_regset_and(*mask, *mask, ztmp);
|
||||
jit_regset_and(&ztmp, mask, &block->reglive);
|
||||
if (jit_regset_set_p(&ztmp)) {
|
||||
jit_regset_ior(live, live, &ztmp);
|
||||
jit_regset_com(&ztmp, &ztmp);
|
||||
jit_regset_and(mask, mask, &ztmp);
|
||||
}
|
||||
break;
|
||||
case jit_code_prolog: case jit_code_epilog:
|
||||
jit_regset_set_ui(*mask, 0);
|
||||
jit_regset_set_ui(mask, 0);
|
||||
return;
|
||||
case jit_code_callr:
|
||||
value = jit_regno(node->u.w);
|
||||
if (!(node->u.w & jit_regno_patch)) {
|
||||
if (jit_regset_tstbit(*mask, value)) {
|
||||
jit_regset_clrbit(*mask, value);
|
||||
jit_regset_setbit(*live, value);
|
||||
if (jit_regset_tstbit(mask, value)) {
|
||||
jit_regset_clrbit(mask, value);
|
||||
jit_regset_setbit(live, value);
|
||||
}
|
||||
}
|
||||
case jit_code_calli:
|
||||
#if defined(JIT_RET)
|
||||
if (jit_regset_tstbit(*mask, JIT_RET)) {
|
||||
jit_regset_setbit(_jitc->reglive, JIT_RET);
|
||||
jit_regset_clrbit(*mask, JIT_RET);
|
||||
if (jit_regset_tstbit(mask, JIT_RET)) {
|
||||
jit_regset_setbit(&_jitc->reglive, JIT_RET);
|
||||
jit_regset_clrbit(mask, JIT_RET);
|
||||
}
|
||||
# if __arm__
|
||||
if (jit_regset_tstbit(*mask, _R1)) {
|
||||
jit_regset_setbit(_jitc->reglive, _R1);
|
||||
jit_regset_clrbit(*mask, _R1);
|
||||
if (jit_regset_tstbit(mask, _R1)) {
|
||||
jit_regset_setbit(&_jitc->reglive, _R1);
|
||||
jit_regset_clrbit(mask, _R1);
|
||||
}
|
||||
# endif
|
||||
#endif
|
||||
#if defined(JIT_FRET)
|
||||
if (jit_regset_tstbit(*mask, JIT_FRET)) {
|
||||
jit_regset_setbit(_jitc->reglive, JIT_FRET);
|
||||
jit_regset_clrbit(*mask, JIT_FRET);
|
||||
if (jit_regset_tstbit(mask, JIT_FRET)) {
|
||||
jit_regset_setbit(&_jitc->reglive, JIT_FRET);
|
||||
jit_regset_clrbit(mask, JIT_FRET);
|
||||
}
|
||||
#endif
|
||||
for (value = 0; value < _jitc->reglen; ++value) {
|
||||
value = jit_regset_scan1(*mask, value);
|
||||
value = jit_regset_scan1(mask, value);
|
||||
if (value >= _jitc->reglen)
|
||||
break;
|
||||
spec = jit_class(_rvs[value].spec);
|
||||
if (!(spec & jit_class_sav))
|
||||
jit_regset_clrbit(*mask, value);
|
||||
jit_regset_clrbit(mask, value);
|
||||
if ((spec & jit_class_arg) && jit_regarg_p(node, value))
|
||||
jit_regset_setbit(*live, value);
|
||||
jit_regset_setbit(live, value);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
value = jit_classify(node->code);
|
||||
if (value & jit_cc_a2_reg) {
|
||||
if (!(node->w.w & jit_regno_patch)) {
|
||||
if (jit_regset_tstbit(*mask, node->w.w)) {
|
||||
jit_regset_clrbit(*mask, node->w.w);
|
||||
jit_regset_setbit(*live, node->w.w);
|
||||
if (jit_regset_tstbit(mask, node->w.w)) {
|
||||
jit_regset_clrbit(mask, node->w.w);
|
||||
jit_regset_setbit(live, node->w.w);
|
||||
}
|
||||
}
|
||||
}
|
||||
if (value & jit_cc_a1_reg) {
|
||||
if (!(node->v.w & jit_regno_patch)) {
|
||||
if (jit_regset_tstbit(*mask, node->v.w)) {
|
||||
jit_regset_clrbit(*mask, node->v.w);
|
||||
if (jit_regset_tstbit(mask, node->v.w)) {
|
||||
jit_regset_clrbit(mask, node->v.w);
|
||||
if (!(value & jit_cc_a1_chg))
|
||||
jit_regset_setbit(*live, node->v.w);
|
||||
jit_regset_setbit(live, node->v.w);
|
||||
}
|
||||
}
|
||||
}
|
||||
if (value & jit_cc_a0_reg) {
|
||||
if (value & jit_cc_a0_rlh) {
|
||||
if (!(node->u.q.l & jit_regno_patch)) {
|
||||
if (jit_regset_tstbit(*mask, node->u.q.l)) {
|
||||
jit_regset_clrbit(*mask, node->u.q.l);
|
||||
if (jit_regset_tstbit(mask, node->u.q.l)) {
|
||||
jit_regset_clrbit(mask, node->u.q.l);
|
||||
if (!(value & jit_cc_a0_chg))
|
||||
jit_regset_setbit(*live, node->u.q.l);
|
||||
jit_regset_setbit(live, node->u.q.l);
|
||||
}
|
||||
}
|
||||
if (!(node->u.q.h & jit_regno_patch)) {
|
||||
if (jit_regset_tstbit(*mask, node->u.q.h)) {
|
||||
jit_regset_clrbit(*mask, node->u.q.h);
|
||||
if (jit_regset_tstbit(mask, node->u.q.h)) {
|
||||
jit_regset_clrbit(mask, node->u.q.h);
|
||||
if (!(value & jit_cc_a0_chg))
|
||||
jit_regset_setbit(*live, node->u.q.h);
|
||||
jit_regset_setbit(live, node->u.q.h);
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
if (!(node->u.w & jit_regno_patch)) {
|
||||
if (jit_regset_tstbit(*mask, node->u.w)) {
|
||||
jit_regset_clrbit(*mask, node->u.w);
|
||||
if (jit_regset_tstbit(mask, node->u.w)) {
|
||||
jit_regset_clrbit(mask, node->u.w);
|
||||
if (!(value & jit_cc_a0_chg))
|
||||
jit_regset_setbit(*live, node->u.w);
|
||||
jit_regset_setbit(live, node->u.w);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1728,29 +1729,29 @@ _jit_update(jit_state_t *_jit, jit_node_t *node,
|
|||
if (bmp_tst(label->v.w))
|
||||
continue;
|
||||
bmp_set(label->v.w);
|
||||
jit_regset_and(ztmp, *mask, block->reglive);
|
||||
if (jit_regset_set_p(ztmp)) {
|
||||
jit_regset_ior(*live, *live, ztmp);
|
||||
jit_regset_com(ztmp, ztmp);
|
||||
jit_regset_and(*mask, *mask, ztmp);
|
||||
jit_regset_and(&ztmp, mask, &block->reglive);
|
||||
if (jit_regset_set_p(&ztmp)) {
|
||||
jit_regset_ior(live, live, &ztmp);
|
||||
jit_regset_com(&ztmp, &ztmp);
|
||||
jit_regset_and(mask, mask, &ztmp);
|
||||
}
|
||||
if (jit_regset_set_p(*mask) == 0)
|
||||
if (jit_regset_set_p(mask) == 0)
|
||||
return;
|
||||
/* restore mask if branch is conditional */
|
||||
zmask = *mask;
|
||||
jit_regset_set(&zmask, mask);
|
||||
jit_update(block->label->next, live, &zmask);
|
||||
jit_regset_xor(ztmp, zmask, *mask);
|
||||
jit_regset_xor(&ztmp, &zmask, mask);
|
||||
/* remove known live registers from mask */
|
||||
if (jit_regset_set_p(ztmp)) {
|
||||
jit_regset_and(ztmp, ztmp, *live);
|
||||
jit_regset_com(ztmp, ztmp);
|
||||
jit_regset_and(*mask, *mask, ztmp);
|
||||
if (jit_regset_set_p(&ztmp)) {
|
||||
jit_regset_and(&ztmp, &ztmp, live);
|
||||
jit_regset_com(&ztmp, &ztmp);
|
||||
jit_regset_and(mask, mask, &ztmp);
|
||||
}
|
||||
continue;
|
||||
}
|
||||
/* assume value is live due to jump to unknown location */
|
||||
jit_regset_ior(*live, *live, *mask);
|
||||
jit_regset_set_ui(*mask, 0);
|
||||
jit_regset_ior(live, live, mask);
|
||||
jit_regset_set_ui(mask, 0);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
|
|
@ -2519,11 +2520,11 @@ _register_change_p(jit_state_t *_jit, jit_node_t *node, jit_node_t *link,
|
|||
static jit_bool_t
|
||||
_spill_reglive_p(jit_state_t *_jit, jit_node_t *node, jit_int32_t regno)
|
||||
{
|
||||
if (!jit_regset_tstbit(_jitc->reglive, regno)) {
|
||||
if (!jit_regset_tstbit(&_jitc->reglive, regno)) {
|
||||
bmp_zero();
|
||||
jit_regset_setbit(_jitc->regmask, regno);
|
||||
jit_regset_setbit(&_jitc->regmask, regno);
|
||||
jit_update(node->next, &_jitc->reglive, &_jitc->regmask);
|
||||
if (!jit_regset_tstbit(_jitc->reglive, regno) &&
|
||||
if (!jit_regset_tstbit(&_jitc->reglive, regno) &&
|
||||
register_change_p(node->next, node->link, regno) != jit_reg_change)
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -2568,7 +2569,7 @@ _patch_registers(jit_state_t *_jit)
|
|||
if (value != regno &&
|
||||
((jit_class(_rvs[value].spec) & spec) &
|
||||
~jit_class_arg) == spec &&
|
||||
!jit_regset_tstbit(_jitc->regarg, value) &&
|
||||
!jit_regset_tstbit(&_jitc->regarg, value) &&
|
||||
!spill_reglive_p(node, value))
|
||||
break;
|
||||
}
|
||||
|
|
@ -2580,7 +2581,7 @@ _patch_registers(jit_state_t *_jit)
|
|||
/* mark as live just in case there are nested
|
||||
* register patches, so that next patch will
|
||||
* not want to use the same register */
|
||||
jit_regset_setbit(_jitc->reglive, value);
|
||||
jit_regset_setbit(&_jitc->reglive, value);
|
||||
/* register is not live, just remove spill/reload */
|
||||
node->link->v.w = jit_regload_isdead;
|
||||
del_node(prev, node);
|
||||
|
|
@ -2615,7 +2616,7 @@ _patch_registers(jit_state_t *_jit)
|
|||
regno = jit_regno(node->u.w);
|
||||
if (node->v.w) {
|
||||
if (node->v.w == jit_regload_isdead)
|
||||
jit_regset_clrbit(_jitc->reglive, regno);
|
||||
jit_regset_clrbit(&_jitc->reglive, regno);
|
||||
del_node(prev, node);
|
||||
continue;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue