mirror of
https://git.savannah.gnu.org/git/guile.git
synced 2025-06-06 20:20:20 +02:00
Make it simpler to add support for more than 64 registers.
* include/lightning/jit_private.h, lib/jit_arm.c, lib/jit_mips-cpu.c, lib/jit_mips.c, lib/jit_ppc-cpu.c, lib/jit_ppc.c, lib/jit_print.c, lib/jit_sparc-cpu.c, lib/jit_sparc.c, lib/jit_x86-cpu.c, lib/jit_x86.c, lib/lightning.c: Change all jit_regset macros to take a pointer argument, to avoid structure copies when adding a port to an architecture with more than 64 registers.
This commit is contained in:
parent
066db584c9
commit
7bdd22bd99
13 changed files with 310 additions and 309 deletions
11
ChangeLog
11
ChangeLog
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@ -1,3 +1,14 @@
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2013-04-10 Paulo Andrade <pcpa@gnu.org>
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* include/lightning/jit_private.h, lib/jit_arm.c,
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lib/jit_mips-cpu.c, lib/jit_mips.c, lib/jit_ppc-cpu.c,
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lib/jit_ppc.c, lib/jit_print.c, lib/jit_sparc-cpu.c,
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lib/jit_sparc.c, lib/jit_x86-cpu.c, lib/jit_x86.c,
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lib/lightning.c: Change all jit_regset macros to take
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a pointer argument, to avoid structure copies when
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adding a port to an architecture with more than 64
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registers.
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2013-04-08 Paulo Andrade <pcpa@gnu.org>
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2013-04-08 Paulo Andrade <pcpa@gnu.org>
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* lib/jit_arm.c, lib/jit_ppc.c: Do not rely on __clear_cache
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* lib/jit_arm.c, lib/jit_ppc.c: Do not rely on __clear_cache
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@ -78,9 +78,9 @@
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#define jit_size(vector) (sizeof(vector) / sizeof((vector)[0]))
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#define jit_size(vector) (sizeof(vector) / sizeof((vector)[0]))
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#define jit_reg_free_p(regno) \
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#define jit_reg_free_p(regno) \
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(!jit_regset_tstbit(_jitc->reglive, regno) && \
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(!jit_regset_tstbit(&_jitc->reglive, regno) && \
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!jit_regset_tstbit(_jitc->regarg, regno) && \
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!jit_regset_tstbit(&_jitc->regarg, regno) && \
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!jit_regset_tstbit(_jitc->regsav, regno))
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!jit_regset_tstbit(&_jitc->regsav, regno))
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/*
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/*
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* Private jit_class bitmasks
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* Private jit_class bitmasks
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@ -121,38 +121,27 @@
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#define jit_cc_a2_flt 0x00200000 /* arg2 is immediate float */
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#define jit_cc_a2_flt 0x00200000 /* arg2 is immediate float */
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#define jit_cc_a2_dbl 0x00400000 /* arg2 is immediate double */
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#define jit_cc_a2_dbl 0x00400000 /* arg2 is immediate double */
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#define jit_regset_com(u, v) ((u) = ~(v))
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#define jit_regset_com(u, v) (*(u) = ~*(v))
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#define jit_regset_and(u, v, w) ((u) = (v) & (w))
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#define jit_regset_and(u, v, w) (*(u) = *(v) & *(w))
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#define jit_regset_ior(u, v, w) ((u) = (v) | (w))
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#define jit_regset_ior(u, v, w) (*(u) = *(v) | *(w))
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#define jit_regset_xor(u, v, w) ((u) = (v) ^ (w))
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#define jit_regset_xor(u, v, w) (*(u) = *(v) ^ *(w))
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#define jit_regset_set(u, v) ((u) = (v))
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#define jit_regset_set(u, v) (*(u) = *(v))
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#define jit_regset_cmp_ui(u, v) ((u) != (v))
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#define jit_regset_set_mask(u, v) (*(u) = (1LL << (v)) - 1)
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#define jit_regset_set_ui(u, v) ((u) = (v))
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#define jit_regset_cmp_ui(u, v) (*(u) != (v))
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#define jit_regset_set_p(set) (set)
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#define jit_regset_set_ui(u, v) (*(u) = (v))
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#if DEBUG
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#define jit_regset_set_p(set) (*set)
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# define jit_regset_clrbit(set, bit) \
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#define jit_regset_clrbit(set, bit) (*(set) &= ~(1LL << (bit)))
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(assert(bit >= 0 && bit < (sizeof(jit_regset_t) << 3)), \
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#define jit_regset_setbit(set, bit) (*(set) |= 1LL << (bit))
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(set) &= ~(1LL << (bit)))
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#define jit_regset_tstbit(set, bit) (*(set) & (1LL << (bit)))
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# define jit_regset_setbit(set, bit) \
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#define jit_regset_new(set) (*(set) = 0)
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(assert(bit >= 0 && bit < (sizeof(jit_regset_t) << 3)), \
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#define jit_regset_del(set) (*(set) = 0)
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(set) |= 1LL << (bit))
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# define jit_regset_tstbit(set, bit) \
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(assert(bit >= 0 && bit < (sizeof(jit_regset_t) << 3)), \
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(set) & (1LL << (bit)))
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#else
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# define jit_regset_clrbit(set, bit) ((set) &= ~(1LL << (bit)))
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# define jit_regset_setbit(set, bit) ((set) |= 1LL << (bit))
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# define jit_regset_tstbit(set, bit) ((set) & (1LL << (bit)))
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#endif
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#define jit_regset_new(set) ((set) = 0)
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#define jit_regset_del(set) ((set) = 0)
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extern unsigned long
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extern unsigned long
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jit_regset_scan1(jit_regset_t, jit_int32_t);
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jit_regset_scan1(jit_regset_t*, jit_int32_t);
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#define jit_reglive_setup() \
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#define jit_reglive_setup() \
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do { \
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do { \
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jit_regset_set_ui(_jitc->reglive, 0); \
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jit_regset_set_ui(&_jitc->reglive, 0); \
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jit_regset_set_ui(_jitc->regmask, 0); \
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jit_regset_set_ui(&_jitc->regmask, 0); \
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} while (0)
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} while (0)
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/*
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/*
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@ -211,8 +211,8 @@ _jit_prolog(jit_state_t *_jit)
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if (_jitc->function)
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if (_jitc->function)
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jit_epilog();
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jit_epilog();
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assert(jit_regset_cmp_ui(_jitc->regarg, 0) == 0);
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assert(jit_regset_cmp_ui(&_jitc->regarg, 0) == 0);
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jit_regset_set_ui(_jitc->regsav, 0);
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jit_regset_set_ui(&_jitc->regsav, 0);
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offset = _jitc->functions.offset;
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offset = _jitc->functions.offset;
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if (offset >= _jitc->functions.length) {
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if (offset >= _jitc->functions.length) {
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jit_realloc((jit_pointer_t *)&_jitc->functions.ptr,
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jit_realloc((jit_pointer_t *)&_jitc->functions.ptr,
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@ -245,7 +245,7 @@ _jit_prolog(jit_state_t *_jit)
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*/
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*/
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_jitc->function->epilog->w.w = offset;
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_jitc->function->epilog->w.w = offset;
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jit_regset_new(_jitc->function->regset);
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jit_regset_new(&_jitc->function->regset);
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}
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}
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jit_int32_t
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jit_int32_t
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@ -1613,28 +1613,28 @@ _jit_get_reg_pair(jit_state_t *_jit)
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* return JIT_NOREG if fail, as the cost of spills is greater
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* return JIT_NOREG if fail, as the cost of spills is greater
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* than splitting a double load/store in two operations. */
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* than splitting a double load/store in two operations. */
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if (jit_reg_free_p(_R0) && jit_reg_free_p(_R1)) {
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if (jit_reg_free_p(_R0) && jit_reg_free_p(_R1)) {
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jit_regset_setbit(_jitc->regarg, _R0);
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jit_regset_setbit(&_jitc->regarg, _R0);
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jit_regset_setbit(_jitc->regarg, _R1);
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jit_regset_setbit(&_jitc->regarg, _R1);
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return (_R0);
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return (_R0);
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}
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}
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if (jit_reg_free_p(_R2) && jit_reg_free_p(_R3)) {
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if (jit_reg_free_p(_R2) && jit_reg_free_p(_R3)) {
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jit_regset_setbit(_jitc->regarg, _R2);
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jit_regset_setbit(&_jitc->regarg, _R2);
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jit_regset_setbit(_jitc->regarg, _R3);
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jit_regset_setbit(&_jitc->regarg, _R3);
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return (_R2);
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return (_R2);
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}
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}
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if (jit_reg_free_p(_R4) && jit_reg_free_p(_R5)) {
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if (jit_reg_free_p(_R4) && jit_reg_free_p(_R5)) {
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jit_regset_setbit(_jitc->regarg, _R4);
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jit_regset_setbit(&_jitc->regarg, _R4);
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jit_regset_setbit(_jitc->regarg, _R5);
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jit_regset_setbit(&_jitc->regarg, _R5);
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return (_R4);
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return (_R4);
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}
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}
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if (jit_reg_free_p(_R6) && jit_reg_free_p(_R7)) {
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if (jit_reg_free_p(_R6) && jit_reg_free_p(_R7)) {
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jit_regset_setbit(_jitc->regarg, _R6);
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jit_regset_setbit(&_jitc->regarg, _R6);
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jit_regset_setbit(_jitc->regarg, _R7);
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jit_regset_setbit(&_jitc->regarg, _R7);
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return (_R6);
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return (_R6);
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}
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}
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if (jit_reg_free_p(_R8) && jit_reg_free_p(_R9)) {
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if (jit_reg_free_p(_R8) && jit_reg_free_p(_R9)) {
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jit_regset_setbit(_jitc->regarg, _R8);
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jit_regset_setbit(&_jitc->regarg, _R8);
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jit_regset_setbit(_jitc->regarg, _R9);
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jit_regset_setbit(&_jitc->regarg, _R9);
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return (_R8);
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return (_R8);
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}
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}
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return (JIT_NOREG);
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return (JIT_NOREG);
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@ -2781,71 +2781,71 @@ _prolog(jit_state_t *_jit, jit_node_t *node)
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/* callee save registers */
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/* callee save registers */
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subi(_SP_REGNO, _SP_REGNO, stack_framesize);
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subi(_SP_REGNO, _SP_REGNO, stack_framesize);
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#if __WORDSIZE == 32
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#if __WORDSIZE == 32
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if (jit_regset_tstbit(_jitc->function->regset, _F30))
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if (jit_regset_tstbit(&_jitc->function->regset, _F30))
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stxi_d(96, _SP_REGNO, _F30_REGNO);
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stxi_d(96, _SP_REGNO, _F30_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _F28))
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if (jit_regset_tstbit(&_jitc->function->regset, _F28))
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stxi_d(88, _SP_REGNO, _F28_REGNO);
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stxi_d(88, _SP_REGNO, _F28_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _F26))
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if (jit_regset_tstbit(&_jitc->function->regset, _F26))
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stxi_d(80, _SP_REGNO, _F26_REGNO);
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stxi_d(80, _SP_REGNO, _F26_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _F24))
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if (jit_regset_tstbit(&_jitc->function->regset, _F24))
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stxi_d(72, _SP_REGNO, _F24_REGNO);
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stxi_d(72, _SP_REGNO, _F24_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _F22))
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if (jit_regset_tstbit(&_jitc->function->regset, _F22))
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stxi_d(64, _SP_REGNO, _F22_REGNO);
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stxi_d(64, _SP_REGNO, _F22_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _F20))
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if (jit_regset_tstbit(&_jitc->function->regset, _F20))
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stxi_d(56, _SP_REGNO, _F20_REGNO);
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stxi_d(56, _SP_REGNO, _F20_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _F18))
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if (jit_regset_tstbit(&_jitc->function->regset, _F18))
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stxi_d(48, _SP_REGNO, _F18_REGNO);
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stxi_d(48, _SP_REGNO, _F18_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _F16))
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if (jit_regset_tstbit(&_jitc->function->regset, _F16))
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stxi_d(40, _SP_REGNO, _F16_REGNO);
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stxi_d(40, _SP_REGNO, _F16_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _S7))
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if (jit_regset_tstbit(&_jitc->function->regset, _S7))
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stxi(36, _SP_REGNO, _S7_REGNO);
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stxi(36, _SP_REGNO, _S7_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _S6))
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if (jit_regset_tstbit(&_jitc->function->regset, _S6))
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stxi(32, _SP_REGNO, _S6_REGNO);
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stxi(32, _SP_REGNO, _S6_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _S5))
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if (jit_regset_tstbit(&_jitc->function->regset, _S5))
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stxi(28, _SP_REGNO, _S5_REGNO);
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stxi(28, _SP_REGNO, _S5_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _S4))
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if (jit_regset_tstbit(&_jitc->function->regset, _S4))
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stxi(24, _SP_REGNO, _S4_REGNO);
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stxi(24, _SP_REGNO, _S4_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _S3))
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if (jit_regset_tstbit(&_jitc->function->regset, _S3))
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stxi(20, _SP_REGNO, _S3_REGNO);
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stxi(20, _SP_REGNO, _S3_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _S2))
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if (jit_regset_tstbit(&_jitc->function->regset, _S2))
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stxi(16, _SP_REGNO, _S2_REGNO);
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stxi(16, _SP_REGNO, _S2_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _S1))
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if (jit_regset_tstbit(&_jitc->function->regset, _S1))
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stxi(12, _SP_REGNO, _S1_REGNO);
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stxi(12, _SP_REGNO, _S1_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _S0))
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if (jit_regset_tstbit(&_jitc->function->regset, _S0))
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stxi( 8, _SP_REGNO, _S0_REGNO);
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stxi( 8, _SP_REGNO, _S0_REGNO);
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stxi( 4, _SP_REGNO, _RA_REGNO);
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stxi( 4, _SP_REGNO, _RA_REGNO);
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#else
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#else
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if (jit_regset_tstbit(_jitc->function->regset, _F30))
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if (jit_regset_tstbit(&_jitc->function->regset, _F30))
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stxi_d(136, _SP_REGNO, _F30_REGNO);
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stxi_d(136, _SP_REGNO, _F30_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _F28))
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if (jit_regset_tstbit(&_jitc->function->regset, _F28))
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stxi_d(128, _SP_REGNO, _F28_REGNO);
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stxi_d(128, _SP_REGNO, _F28_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _F26))
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if (jit_regset_tstbit(&_jitc->function->regset, _F26))
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stxi_d(120, _SP_REGNO, _F26_REGNO);
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stxi_d(120, _SP_REGNO, _F26_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _F24))
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if (jit_regset_tstbit(&_jitc->function->regset, _F24))
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stxi_d(112, _SP_REGNO, _F24_REGNO);
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stxi_d(112, _SP_REGNO, _F24_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _F22))
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if (jit_regset_tstbit(&_jitc->function->regset, _F22))
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stxi_d(104, _SP_REGNO, _F22_REGNO);
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stxi_d(104, _SP_REGNO, _F22_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _F20))
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if (jit_regset_tstbit(&_jitc->function->regset, _F20))
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stxi_d(96, _SP_REGNO, _F20_REGNO);
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stxi_d(96, _SP_REGNO, _F20_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _F18))
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if (jit_regset_tstbit(&_jitc->function->regset, _F18))
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stxi_d(88, _SP_REGNO, _F18_REGNO);
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stxi_d(88, _SP_REGNO, _F18_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _F16))
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if (jit_regset_tstbit(&_jitc->function->regset, _F16))
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stxi_d(80, _SP_REGNO, _F16_REGNO);
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stxi_d(80, _SP_REGNO, _F16_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _S7))
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if (jit_regset_tstbit(&_jitc->function->regset, _S7))
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stxi(72, _SP_REGNO, _S7_REGNO);
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stxi(72, _SP_REGNO, _S7_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _S6))
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if (jit_regset_tstbit(&_jitc->function->regset, _S6))
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stxi(64, _SP_REGNO, _S6_REGNO);
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stxi(64, _SP_REGNO, _S6_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _S5))
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if (jit_regset_tstbit(&_jitc->function->regset, _S5))
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stxi(56, _SP_REGNO, _S5_REGNO);
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stxi(56, _SP_REGNO, _S5_REGNO);
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if (jit_regset_tstbit(_jitc->function->regset, _S4))
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if (jit_regset_tstbit(&_jitc->function->regset, _S4))
|
||||||
stxi(48, _SP_REGNO, _S4_REGNO);
|
stxi(48, _SP_REGNO, _S4_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S3))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S3))
|
||||||
stxi(40, _SP_REGNO, _S3_REGNO);
|
stxi(40, _SP_REGNO, _S3_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S2))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S2))
|
||||||
stxi(32, _SP_REGNO, _S2_REGNO);
|
stxi(32, _SP_REGNO, _S2_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S1))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S1))
|
||||||
stxi(24, _SP_REGNO, _S1_REGNO);
|
stxi(24, _SP_REGNO, _S1_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S0))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S0))
|
||||||
stxi(16, _SP_REGNO, _S0_REGNO);
|
stxi(16, _SP_REGNO, _S0_REGNO);
|
||||||
stxi( 8, _SP_REGNO, _RA_REGNO);
|
stxi( 8, _SP_REGNO, _RA_REGNO);
|
||||||
#endif
|
#endif
|
||||||
|
@ -2862,71 +2862,71 @@ _epilog(jit_state_t *_jit, jit_node_t *node)
|
||||||
/* callee save registers */
|
/* callee save registers */
|
||||||
movr(_SP_REGNO, _BP_REGNO);
|
movr(_SP_REGNO, _BP_REGNO);
|
||||||
#if __WORDSIZE == 32
|
#if __WORDSIZE == 32
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F30))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F30))
|
||||||
ldxi_d(_F30_REGNO, _SP_REGNO, 96);
|
ldxi_d(_F30_REGNO, _SP_REGNO, 96);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F28))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F28))
|
||||||
ldxi_d(_F28_REGNO, _SP_REGNO, 88);
|
ldxi_d(_F28_REGNO, _SP_REGNO, 88);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F26))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F26))
|
||||||
ldxi_d(_F26_REGNO, _SP_REGNO, 80);
|
ldxi_d(_F26_REGNO, _SP_REGNO, 80);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F24))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F24))
|
||||||
ldxi_d(_F24_REGNO, _SP_REGNO, 72);
|
ldxi_d(_F24_REGNO, _SP_REGNO, 72);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F22))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F22))
|
||||||
ldxi_d(_F22_REGNO, _SP_REGNO, 64);
|
ldxi_d(_F22_REGNO, _SP_REGNO, 64);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F20))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F20))
|
||||||
ldxi_d(_F20_REGNO, _SP_REGNO, 56);
|
ldxi_d(_F20_REGNO, _SP_REGNO, 56);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F18))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F18))
|
||||||
ldxi_d(_F18_REGNO, _SP_REGNO, 48);
|
ldxi_d(_F18_REGNO, _SP_REGNO, 48);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F16))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F16))
|
||||||
ldxi_d(_F16_REGNO, _SP_REGNO, 40);
|
ldxi_d(_F16_REGNO, _SP_REGNO, 40);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S7))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S7))
|
||||||
ldxi(_S7_REGNO, _SP_REGNO, 36);
|
ldxi(_S7_REGNO, _SP_REGNO, 36);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S6))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S6))
|
||||||
ldxi(_S6_REGNO, _SP_REGNO, 32);
|
ldxi(_S6_REGNO, _SP_REGNO, 32);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S5))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S5))
|
||||||
ldxi(_S5_REGNO, _SP_REGNO, 28);
|
ldxi(_S5_REGNO, _SP_REGNO, 28);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S4))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S4))
|
||||||
ldxi(_S4_REGNO, _SP_REGNO, 24);
|
ldxi(_S4_REGNO, _SP_REGNO, 24);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S3))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S3))
|
||||||
ldxi(_S3_REGNO, _SP_REGNO, 20);
|
ldxi(_S3_REGNO, _SP_REGNO, 20);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S2))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S2))
|
||||||
ldxi(_S2_REGNO, _SP_REGNO, 16);
|
ldxi(_S2_REGNO, _SP_REGNO, 16);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S1))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S1))
|
||||||
ldxi(_S1_REGNO, _SP_REGNO, 12);
|
ldxi(_S1_REGNO, _SP_REGNO, 12);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S0))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S0))
|
||||||
ldxi(_S0_REGNO, _SP_REGNO, 8);
|
ldxi(_S0_REGNO, _SP_REGNO, 8);
|
||||||
ldxi(_RA_REGNO, _SP_REGNO, 4);
|
ldxi(_RA_REGNO, _SP_REGNO, 4);
|
||||||
#else
|
#else
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F30))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F30))
|
||||||
ldxi_d(_F30_REGNO, _SP_REGNO, 136);
|
ldxi_d(_F30_REGNO, _SP_REGNO, 136);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F28))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F28))
|
||||||
ldxi_d(_F28_REGNO, _SP_REGNO, 128);
|
ldxi_d(_F28_REGNO, _SP_REGNO, 128);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F26))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F26))
|
||||||
ldxi_d(_F26_REGNO, _SP_REGNO, 120);
|
ldxi_d(_F26_REGNO, _SP_REGNO, 120);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F24))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F24))
|
||||||
ldxi_d(_F24_REGNO, _SP_REGNO, 112);
|
ldxi_d(_F24_REGNO, _SP_REGNO, 112);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F22))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F22))
|
||||||
ldxi_d(_F22_REGNO, _SP_REGNO, 104);
|
ldxi_d(_F22_REGNO, _SP_REGNO, 104);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F20))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F20))
|
||||||
ldxi_d(_F20_REGNO, _SP_REGNO, 96);
|
ldxi_d(_F20_REGNO, _SP_REGNO, 96);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F18))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F18))
|
||||||
ldxi_d(_F18_REGNO, _SP_REGNO, 88);
|
ldxi_d(_F18_REGNO, _SP_REGNO, 88);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F16))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F16))
|
||||||
ldxi_d(_F16_REGNO, _SP_REGNO, 80);
|
ldxi_d(_F16_REGNO, _SP_REGNO, 80);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S7))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S7))
|
||||||
ldxi(_S7_REGNO, _SP_REGNO, 72);
|
ldxi(_S7_REGNO, _SP_REGNO, 72);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S6))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S6))
|
||||||
ldxi(_S6_REGNO, _SP_REGNO, 64);
|
ldxi(_S6_REGNO, _SP_REGNO, 64);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S5))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S5))
|
||||||
ldxi(_S5_REGNO, _SP_REGNO, 56);
|
ldxi(_S5_REGNO, _SP_REGNO, 56);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S4))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S4))
|
||||||
ldxi(_S4_REGNO, _SP_REGNO, 48);
|
ldxi(_S4_REGNO, _SP_REGNO, 48);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S3))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S3))
|
||||||
ldxi(_S3_REGNO, _SP_REGNO, 40);
|
ldxi(_S3_REGNO, _SP_REGNO, 40);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S2))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S2))
|
||||||
ldxi(_S2_REGNO, _SP_REGNO, 32);
|
ldxi(_S2_REGNO, _SP_REGNO, 32);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S1))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S1))
|
||||||
ldxi(_S1_REGNO, _SP_REGNO, 24);
|
ldxi(_S1_REGNO, _SP_REGNO, 24);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _S0))
|
if (jit_regset_tstbit(&_jitc->function->regset, _S0))
|
||||||
ldxi(_S0_REGNO, _SP_REGNO, 16);
|
ldxi(_S0_REGNO, _SP_REGNO, 16);
|
||||||
ldxi(_RA_REGNO, _SP_REGNO, 8);
|
ldxi(_RA_REGNO, _SP_REGNO, 8);
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -120,8 +120,8 @@ _jit_prolog(jit_state_t *_jit)
|
||||||
|
|
||||||
if (_jitc->function)
|
if (_jitc->function)
|
||||||
jit_epilog();
|
jit_epilog();
|
||||||
assert(jit_regset_cmp_ui(_jitc->regarg, 0) == 0);
|
assert(jit_regset_cmp_ui(&_jitc->regarg, 0) == 0);
|
||||||
jit_regset_set_ui(_jitc->regsav, 0);
|
jit_regset_set_ui(&_jitc->regsav, 0);
|
||||||
offset = _jitc->functions.offset;
|
offset = _jitc->functions.offset;
|
||||||
if (offset >= _jitc->functions.length) {
|
if (offset >= _jitc->functions.length) {
|
||||||
jit_realloc((jit_pointer_t *)&_jitc->functions.ptr,
|
jit_realloc((jit_pointer_t *)&_jitc->functions.ptr,
|
||||||
|
@ -147,7 +147,7 @@ _jit_prolog(jit_state_t *_jit)
|
||||||
*/
|
*/
|
||||||
_jitc->function->epilog->w.w = offset;
|
_jitc->function->epilog->w.w = offset;
|
||||||
|
|
||||||
jit_regset_new(_jitc->function->regset);
|
jit_regset_new(&_jitc->function->regset);
|
||||||
}
|
}
|
||||||
|
|
||||||
jit_int32_t
|
jit_int32_t
|
||||||
|
|
|
@ -3076,12 +3076,12 @@ _prolog(jit_state_t *_jit, jit_node_t *node)
|
||||||
|
|
||||||
# if __WORDSIZE == 32
|
# if __WORDSIZE == 32
|
||||||
/* save any clobbered callee save gpr register */
|
/* save any clobbered callee save gpr register */
|
||||||
regno = jit_regset_scan1(_jitc->function->regset, _R14);
|
regno = jit_regset_scan1(&_jitc->function->regset, _R14);
|
||||||
if (regno == ULONG_MAX || regno > _R31)
|
if (regno == ULONG_MAX || regno > _R31)
|
||||||
regno = _R31; /* aka _FP_REGNO */
|
regno = _R31; /* aka _FP_REGNO */
|
||||||
STMW(rn(regno), _SP_REGNO, -fpr_save_area - (32 * 4) + rn(regno) * 4);
|
STMW(rn(regno), _SP_REGNO, -fpr_save_area - (32 * 4) + rn(regno) * 4);
|
||||||
for (offset = 0; offset < 8; offset++) {
|
for (offset = 0; offset < 8; offset++) {
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F14 + offset))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F14 + offset))
|
||||||
stxi_d(-fpr_save_area + offset * 8, _SP_REGNO, rn(_F14 + offset));
|
stxi_d(-fpr_save_area + offset * 8, _SP_REGNO, rn(_F14 + offset));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -3093,11 +3093,11 @@ _prolog(jit_state_t *_jit, jit_node_t *node)
|
||||||
stxi(16, _SP_REGNO, _R0_REGNO);
|
stxi(16, _SP_REGNO, _R0_REGNO);
|
||||||
offset = -144;
|
offset = -144;
|
||||||
for (regno = 0; regno < jit_size(save); regno++, offset += 8) {
|
for (regno = 0; regno < jit_size(save); regno++, offset += 8) {
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, save[regno]))
|
if (jit_regset_tstbit(&_jitc->function->regset, save[regno]))
|
||||||
stxi(offset, _SP_REGNO, rn(save[regno]));
|
stxi(offset, _SP_REGNO, rn(save[regno]));
|
||||||
}
|
}
|
||||||
for (offset = 0; offset < 8; offset++) {
|
for (offset = 0; offset < 8; offset++) {
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F14 + offset))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F14 + offset))
|
||||||
stxi_d(-(152 + offset * 8), _SP_REGNO, rn(_F14 + offset));
|
stxi_d(-(152 + offset * 8), _SP_REGNO, rn(_F14 + offset));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -3119,12 +3119,12 @@ _epilog(jit_state_t *_jit, jit_node_t *node)
|
||||||
|
|
||||||
MTLR(_R0_REGNO);
|
MTLR(_R0_REGNO);
|
||||||
|
|
||||||
regno = jit_regset_scan1(_jitc->function->regset, _R14);
|
regno = jit_regset_scan1(&_jitc->function->regset, _R14);
|
||||||
if (regno == ULONG_MAX || regno > _R31)
|
if (regno == ULONG_MAX || regno > _R31)
|
||||||
regno = _R31; /* aka _FP_REGNO */
|
regno = _R31; /* aka _FP_REGNO */
|
||||||
LMW(rn(regno), _SP_REGNO, -fpr_save_area - (32 * 4) + rn(regno) * 4);
|
LMW(rn(regno), _SP_REGNO, -fpr_save_area - (32 * 4) + rn(regno) * 4);
|
||||||
for (offset = 0; offset < 8; offset++) {
|
for (offset = 0; offset < 8; offset++) {
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F14 + offset))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F14 + offset))
|
||||||
ldxi_d(rn(_F14 + offset), _SP_REGNO, -fpr_save_area + offset * 8);
|
ldxi_d(rn(_F14 + offset), _SP_REGNO, -fpr_save_area + offset * 8);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -3133,11 +3133,11 @@ _epilog(jit_state_t *_jit, jit_node_t *node)
|
||||||
ldxi(_R0_REGNO, _SP_REGNO, 16);
|
ldxi(_R0_REGNO, _SP_REGNO, 16);
|
||||||
offset = -144;
|
offset = -144;
|
||||||
for (regno = 0; regno < jit_size(save); regno++, offset += 8) {
|
for (regno = 0; regno < jit_size(save); regno++, offset += 8) {
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, save[regno]))
|
if (jit_regset_tstbit(&_jitc->function->regset, save[regno]))
|
||||||
ldxi(rn(save[regno]), _SP_REGNO, offset);
|
ldxi(rn(save[regno]), _SP_REGNO, offset);
|
||||||
}
|
}
|
||||||
for (offset = 0; offset < 8; offset++) {
|
for (offset = 0; offset < 8; offset++) {
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _F14 + offset))
|
if (jit_regset_tstbit(&_jitc->function->regset, _F14 + offset))
|
||||||
ldxi_d(rn(_F14 + offset), _SP_REGNO, -(152 + offset * 8));
|
ldxi_d(rn(_F14 + offset), _SP_REGNO, -(152 + offset * 8));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -131,8 +131,8 @@ _jit_prolog(jit_state_t *_jit)
|
||||||
|
|
||||||
if (_jitc->function)
|
if (_jitc->function)
|
||||||
jit_epilog();
|
jit_epilog();
|
||||||
assert(jit_regset_cmp_ui(_jitc->regarg, 0) == 0);
|
assert(jit_regset_cmp_ui(&_jitc->regarg, 0) == 0);
|
||||||
jit_regset_set_ui(_jitc->regsav, 0);
|
jit_regset_set_ui(&_jitc->regsav, 0);
|
||||||
offset = _jitc->functions.offset;
|
offset = _jitc->functions.offset;
|
||||||
if (offset >= _jitc->functions.length) {
|
if (offset >= _jitc->functions.length) {
|
||||||
jit_realloc((jit_pointer_t *)&_jitc->functions.ptr,
|
jit_realloc((jit_pointer_t *)&_jitc->functions.ptr,
|
||||||
|
@ -160,7 +160,7 @@ _jit_prolog(jit_state_t *_jit)
|
||||||
*/
|
*/
|
||||||
_jitc->function->epilog->w.w = offset;
|
_jitc->function->epilog->w.w = offset;
|
||||||
|
|
||||||
jit_regset_new(_jitc->function->regset);
|
jit_regset_new(&_jitc->function->regset);
|
||||||
}
|
}
|
||||||
|
|
||||||
jit_int32_t
|
jit_int32_t
|
||||||
|
|
|
@ -239,7 +239,7 @@ _jit_print(jit_state_t *_jit)
|
||||||
print_chr(':');
|
print_chr(':');
|
||||||
block = _jitc->blocks.ptr + node->v.w;
|
block = _jitc->blocks.ptr + node->v.w;
|
||||||
for (offset = 0; offset < _jitc->reglen; offset++) {
|
for (offset = 0; offset < _jitc->reglen; offset++) {
|
||||||
if (jit_regset_tstbit(block->reglive, offset)) {
|
if (jit_regset_tstbit(&block->reglive, offset)) {
|
||||||
print_chr(' ');
|
print_chr(' ');
|
||||||
print_reg(offset);
|
print_reg(offset);
|
||||||
}
|
}
|
||||||
|
|
|
@ -1626,21 +1626,21 @@ _prolog(jit_state_t *_jit, jit_node_t *node)
|
||||||
|
|
||||||
/* (most) other backends do not save incoming arguments, so,
|
/* (most) other backends do not save incoming arguments, so,
|
||||||
* only save locals here */
|
* only save locals here */
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L0))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L0))
|
||||||
stxi(0, _SP_REGNO, _L0_REGNO);
|
stxi(0, _SP_REGNO, _L0_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L1))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L1))
|
||||||
stxi(4, _SP_REGNO, _L1_REGNO);
|
stxi(4, _SP_REGNO, _L1_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L2))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L2))
|
||||||
stxi(8, _SP_REGNO, _L2_REGNO);
|
stxi(8, _SP_REGNO, _L2_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L3))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L3))
|
||||||
stxi(12, _SP_REGNO, _L3_REGNO);
|
stxi(12, _SP_REGNO, _L3_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L4))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L4))
|
||||||
stxi(16, _SP_REGNO, _L4_REGNO);
|
stxi(16, _SP_REGNO, _L4_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L5))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L5))
|
||||||
stxi(20, _SP_REGNO, _L5_REGNO);
|
stxi(20, _SP_REGNO, _L5_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L6))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L6))
|
||||||
stxi(24, _SP_REGNO, _L6_REGNO);
|
stxi(24, _SP_REGNO, _L6_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L7))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L7))
|
||||||
stxi(28, _SP_REGNO, _L7_REGNO);
|
stxi(28, _SP_REGNO, _L7_REGNO);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1649,21 +1649,21 @@ _epilog(jit_state_t *_jit, jit_node_t *node)
|
||||||
{
|
{
|
||||||
/* (most) other backends do not save incoming arguments, so,
|
/* (most) other backends do not save incoming arguments, so,
|
||||||
* only save locals here */
|
* only save locals here */
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L0))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L0))
|
||||||
ldxi(_L0_REGNO, _SP_REGNO, 0);
|
ldxi(_L0_REGNO, _SP_REGNO, 0);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L1))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L1))
|
||||||
ldxi(_L1_REGNO, _SP_REGNO, 4);
|
ldxi(_L1_REGNO, _SP_REGNO, 4);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L2))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L2))
|
||||||
ldxi(_L2_REGNO, _SP_REGNO, 8);
|
ldxi(_L2_REGNO, _SP_REGNO, 8);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L3))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L3))
|
||||||
ldxi(_L3_REGNO, _SP_REGNO, 12);
|
ldxi(_L3_REGNO, _SP_REGNO, 12);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L4))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L4))
|
||||||
ldxi(_L4_REGNO, _SP_REGNO, 16);
|
ldxi(_L4_REGNO, _SP_REGNO, 16);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L5))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L5))
|
||||||
ldxi(_L5_REGNO, _SP_REGNO, 20);
|
ldxi(_L5_REGNO, _SP_REGNO, 20);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L6))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L6))
|
||||||
ldxi(_L6_REGNO, _SP_REGNO, 24);
|
ldxi(_L6_REGNO, _SP_REGNO, 24);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _L7))
|
if (jit_regset_tstbit(&_jitc->function->regset, _L7))
|
||||||
ldxi(_L7_REGNO, _SP_REGNO, 28);
|
ldxi(_L7_REGNO, _SP_REGNO, 28);
|
||||||
RESTOREI(0, 0, 0);
|
RESTOREI(0, 0, 0);
|
||||||
RETL();
|
RETL();
|
||||||
|
|
|
@ -105,8 +105,8 @@ _jit_prolog(jit_state_t *_jit)
|
||||||
|
|
||||||
if (_jitc->function)
|
if (_jitc->function)
|
||||||
jit_epilog();
|
jit_epilog();
|
||||||
assert(jit_regset_cmp_ui(_jitc->regarg, 0) == 0);
|
assert(jit_regset_cmp_ui(&_jitc->regarg, 0) == 0);
|
||||||
jit_regset_set_ui(_jitc->regsav, 0);
|
jit_regset_set_ui(&_jitc->regsav, 0);
|
||||||
offset = _jitc->functions.offset;
|
offset = _jitc->functions.offset;
|
||||||
if (offset >= _jitc->functions.length) {
|
if (offset >= _jitc->functions.length) {
|
||||||
jit_realloc((jit_pointer_t *)&_jitc->functions.ptr,
|
jit_realloc((jit_pointer_t *)&_jitc->functions.ptr,
|
||||||
|
@ -134,7 +134,7 @@ _jit_prolog(jit_state_t *_jit)
|
||||||
*/
|
*/
|
||||||
_jitc->function->epilog->w.w = offset;
|
_jitc->function->epilog->w.w = offset;
|
||||||
|
|
||||||
jit_regset_new(_jitc->function->regset);
|
jit_regset_new(&_jitc->function->regset);
|
||||||
}
|
}
|
||||||
|
|
||||||
jit_int32_t
|
jit_int32_t
|
||||||
|
|
|
@ -867,8 +867,8 @@ _save(jit_state_t *_jit, jit_int32_t r0)
|
||||||
_jitc->function->regoff[r0] = jit_allocai(sizeof(jit_word_t));
|
_jitc->function->regoff[r0] = jit_allocai(sizeof(jit_word_t));
|
||||||
_jitc->again = 1;
|
_jitc->again = 1;
|
||||||
}
|
}
|
||||||
assert(!jit_regset_tstbit(_jitc->regsav, r0));
|
assert(!jit_regset_tstbit(&_jitc->regsav, r0));
|
||||||
jit_regset_setbit(_jitc->regsav, r0);
|
jit_regset_setbit(&_jitc->regsav, r0);
|
||||||
stxi(_jitc->function->regoff[r0], _RBP_REGNO, r0);
|
stxi(_jitc->function->regoff[r0], _RBP_REGNO, r0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -876,8 +876,8 @@ static void
|
||||||
_load(jit_state_t *_jit, jit_int32_t r0)
|
_load(jit_state_t *_jit, jit_int32_t r0)
|
||||||
{
|
{
|
||||||
assert(_jitc->function->regoff[r0]);
|
assert(_jitc->function->regoff[r0]);
|
||||||
assert(jit_regset_tstbit(_jitc->regsav, r0));
|
assert(jit_regset_tstbit(&_jitc->regsav, r0));
|
||||||
jit_regset_clrbit(_jitc->regsav, r0);
|
jit_regset_clrbit(&_jitc->regsav, r0);
|
||||||
ldxi(r0, _RBP_REGNO, _jitc->function->regoff[r0]);
|
ldxi(r0, _RBP_REGNO, _jitc->function->regoff[r0]);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1199,8 +1199,8 @@ _muli(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
|
||||||
if (set & (1 << rn)) \
|
if (set & (1 << rn)) \
|
||||||
(void)jit_get_reg(rv|jit_class_gpr|jit_class_named); \
|
(void)jit_get_reg(rv|jit_class_gpr|jit_class_named); \
|
||||||
if (sav & (1 << rn)) { \
|
if (sav & (1 << rn)) { \
|
||||||
if ( jit_regset_tstbit(_jitc->regsav, rv) || \
|
if ( jit_regset_tstbit(&_jitc->regsav, rv) || \
|
||||||
!jit_regset_tstbit(_jitc->reglive, rv)) \
|
!jit_regset_tstbit(&_jitc->reglive, rv)) \
|
||||||
sav &= ~(1 << rn); \
|
sav &= ~(1 << rn); \
|
||||||
else \
|
else \
|
||||||
save(rv); \
|
save(rv); \
|
||||||
|
@ -3313,22 +3313,22 @@ _prolog(jit_state_t *_jit, jit_node_t *node)
|
||||||
/* callee save registers */
|
/* callee save registers */
|
||||||
subi(_RSP_REGNO, _RSP_REGNO, stack_framesize - sizeof(jit_word_t));
|
subi(_RSP_REGNO, _RSP_REGNO, stack_framesize - sizeof(jit_word_t));
|
||||||
#if __WORDSIZE == 32
|
#if __WORDSIZE == 32
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _RDI))
|
if (jit_regset_tstbit(&_jitc->function->regset, _RDI))
|
||||||
stxi(12, _RSP_REGNO, _RDI_REGNO);
|
stxi(12, _RSP_REGNO, _RDI_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _RSI))
|
if (jit_regset_tstbit(&_jitc->function->regset, _RSI))
|
||||||
stxi( 8, _RSP_REGNO, _RSI_REGNO);
|
stxi( 8, _RSP_REGNO, _RSI_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _RBX))
|
if (jit_regset_tstbit(&_jitc->function->regset, _RBX))
|
||||||
stxi( 4, _RSP_REGNO, _RBX_REGNO);
|
stxi( 4, _RSP_REGNO, _RBX_REGNO);
|
||||||
#else
|
#else
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _RBX))
|
if (jit_regset_tstbit(&_jitc->function->regset, _RBX))
|
||||||
stxi(40, _RSP_REGNO, _RBX_REGNO);
|
stxi(40, _RSP_REGNO, _RBX_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _R12))
|
if (jit_regset_tstbit(&_jitc->function->regset, _R12))
|
||||||
stxi(32, _RSP_REGNO, _R12_REGNO);
|
stxi(32, _RSP_REGNO, _R12_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _R13))
|
if (jit_regset_tstbit(&_jitc->function->regset, _R13))
|
||||||
stxi(24, _RSP_REGNO, _R13_REGNO);
|
stxi(24, _RSP_REGNO, _R13_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _R14))
|
if (jit_regset_tstbit(&_jitc->function->regset, _R14))
|
||||||
stxi(16, _RSP_REGNO, _R14_REGNO);
|
stxi(16, _RSP_REGNO, _R14_REGNO);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _R15))
|
if (jit_regset_tstbit(&_jitc->function->regset, _R15))
|
||||||
stxi( 8, _RSP_REGNO, _R15_REGNO);
|
stxi( 8, _RSP_REGNO, _R15_REGNO);
|
||||||
#endif
|
#endif
|
||||||
stxi(0, _RSP_REGNO, _RBP_REGNO);
|
stxi(0, _RSP_REGNO, _RBP_REGNO);
|
||||||
|
@ -3344,22 +3344,22 @@ _epilog(jit_state_t *_jit, jit_node_t *node)
|
||||||
/* callee save registers */
|
/* callee save registers */
|
||||||
movr(_RSP_REGNO, _RBP_REGNO);
|
movr(_RSP_REGNO, _RBP_REGNO);
|
||||||
#if __WORDSIZE == 32
|
#if __WORDSIZE == 32
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _RDI))
|
if (jit_regset_tstbit(&_jitc->function->regset, _RDI))
|
||||||
ldxi(_RDI_REGNO, _RSP_REGNO, 12);
|
ldxi(_RDI_REGNO, _RSP_REGNO, 12);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _RSI))
|
if (jit_regset_tstbit(&_jitc->function->regset, _RSI))
|
||||||
ldxi(_RSI_REGNO, _RSP_REGNO, 8);
|
ldxi(_RSI_REGNO, _RSP_REGNO, 8);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _RBX))
|
if (jit_regset_tstbit(&_jitc->function->regset, _RBX))
|
||||||
ldxi(_RBX_REGNO, _RSP_REGNO, 4);
|
ldxi(_RBX_REGNO, _RSP_REGNO, 4);
|
||||||
#else
|
#else
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _RBX))
|
if (jit_regset_tstbit(&_jitc->function->regset, _RBX))
|
||||||
ldxi(_RBX_REGNO, _RSP_REGNO, 40);
|
ldxi(_RBX_REGNO, _RSP_REGNO, 40);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _R12))
|
if (jit_regset_tstbit(&_jitc->function->regset, _R12))
|
||||||
ldxi(_R12_REGNO, _RSP_REGNO, 32);
|
ldxi(_R12_REGNO, _RSP_REGNO, 32);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _R13))
|
if (jit_regset_tstbit(&_jitc->function->regset, _R13))
|
||||||
ldxi(_R13_REGNO, _RSP_REGNO, 24);
|
ldxi(_R13_REGNO, _RSP_REGNO, 24);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _R14))
|
if (jit_regset_tstbit(&_jitc->function->regset, _R14))
|
||||||
ldxi(_R14_REGNO, _RSP_REGNO, 16);
|
ldxi(_R14_REGNO, _RSP_REGNO, 16);
|
||||||
if (jit_regset_tstbit(_jitc->function->regset, _R15))
|
if (jit_regset_tstbit(&_jitc->function->regset, _R15))
|
||||||
ldxi(_R15_REGNO, _RSP_REGNO, 8);
|
ldxi(_R15_REGNO, _RSP_REGNO, 8);
|
||||||
#endif
|
#endif
|
||||||
ldxi(_RBP_REGNO, _RSP_REGNO, 0);
|
ldxi(_RBP_REGNO, _RSP_REGNO, 0);
|
||||||
|
|
|
@ -294,8 +294,8 @@ _jit_prolog(jit_state_t *_jit)
|
||||||
|
|
||||||
if (_jitc->function)
|
if (_jitc->function)
|
||||||
jit_epilog();
|
jit_epilog();
|
||||||
assert(jit_regset_cmp_ui(_jitc->regarg, 0) == 0);
|
assert(jit_regset_cmp_ui(&_jitc->regarg, 0) == 0);
|
||||||
jit_regset_set_ui(_jitc->regsav, 0);
|
jit_regset_set_ui(&_jitc->regsav, 0);
|
||||||
offset = _jitc->functions.offset;
|
offset = _jitc->functions.offset;
|
||||||
if (offset >= _jitc->functions.length) {
|
if (offset >= _jitc->functions.length) {
|
||||||
jit_realloc((jit_pointer_t *)&_jitc->functions.ptr,
|
jit_realloc((jit_pointer_t *)&_jitc->functions.ptr,
|
||||||
|
@ -323,7 +323,7 @@ _jit_prolog(jit_state_t *_jit)
|
||||||
*/
|
*/
|
||||||
_jitc->function->epilog->w.w = offset;
|
_jitc->function->epilog->w.w = offset;
|
||||||
|
|
||||||
jit_regset_new(_jitc->function->regset);
|
jit_regset_new(&_jitc->function->regset);
|
||||||
}
|
}
|
||||||
|
|
||||||
jit_int32_t
|
jit_int32_t
|
||||||
|
@ -784,13 +784,13 @@ _jit_finishi(jit_state_t *_jit, jit_pointer_t i0)
|
||||||
* registers, and not save/restore it, what would be wrong if using the
|
* registers, and not save/restore it, what would be wrong if using the
|
||||||
* the return value, otherwise, just a needless noop */
|
* the return value, otherwise, just a needless noop */
|
||||||
/* >> prevent %rax from being allocated as the function pointer */
|
/* >> prevent %rax from being allocated as the function pointer */
|
||||||
jit_regset_setbit(_jitc->regarg, _RAX);
|
jit_regset_setbit(&_jitc->regarg, _RAX);
|
||||||
reg = jit_get_reg(jit_class_gpr);
|
reg = jit_get_reg(jit_class_gpr);
|
||||||
node = jit_movi(reg, (jit_word_t)i0);
|
node = jit_movi(reg, (jit_word_t)i0);
|
||||||
jit_finishr(reg);
|
jit_finishr(reg);
|
||||||
jit_unget_reg(reg);
|
jit_unget_reg(reg);
|
||||||
/* << prevent %rax from being allocated as the function pointer */
|
/* << prevent %rax from being allocated as the function pointer */
|
||||||
jit_regset_clrbit(_jitc->regarg, _RAX);
|
jit_regset_clrbit(&_jitc->regarg, _RAX);
|
||||||
#else
|
#else
|
||||||
node = jit_calli(i0);
|
node = jit_calli(i0);
|
||||||
node->v.w = _jitc->function->call.argi;
|
node->v.w = _jitc->function->call.argi;
|
||||||
|
|
281
lib/lightning.c
281
lib/lightning.c
|
@ -182,19 +182,19 @@ _jit_get_reg(jit_state_t *_jit, jit_int32_t regspec)
|
||||||
spec = regspec & ~(jit_class_chk|jit_class_nospill);
|
spec = regspec & ~(jit_class_chk|jit_class_nospill);
|
||||||
if (spec & jit_class_named) {
|
if (spec & jit_class_named) {
|
||||||
regno = jit_regno(spec);
|
regno = jit_regno(spec);
|
||||||
if (jit_regset_tstbit(_jitc->regsav, regno))
|
if (jit_regset_tstbit(&_jitc->regsav, regno))
|
||||||
/* fail if register is spilled */
|
/* fail if register is spilled */
|
||||||
goto fail;
|
goto fail;
|
||||||
if (jit_regset_tstbit(_jitc->regarg, regno))
|
if (jit_regset_tstbit(&_jitc->regarg, regno))
|
||||||
/* fail if register is an argument to current instruction */
|
/* fail if register is an argument to current instruction */
|
||||||
goto fail;
|
goto fail;
|
||||||
if (jit_regset_tstbit(_jitc->reglive, regno)) {
|
if (jit_regset_tstbit(&_jitc->reglive, regno)) {
|
||||||
if (regspec & jit_class_nospill)
|
if (regspec & jit_class_nospill)
|
||||||
/* fail if register is live and should not spill/reload */
|
/* fail if register is live and should not spill/reload */
|
||||||
goto fail;
|
goto fail;
|
||||||
goto spill;
|
goto spill;
|
||||||
}
|
}
|
||||||
jit_regset_setbit(_jitc->regarg, regno);
|
jit_regset_setbit(&_jitc->regarg, regno);
|
||||||
return (regno);
|
return (regno);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
|
@ -204,8 +204,8 @@ _jit_get_reg(jit_state_t *_jit, jit_int32_t regspec)
|
||||||
/* search for a free register matching spec */
|
/* search for a free register matching spec */
|
||||||
for (regno = 0; regno < _jitc->reglen; regno++) {
|
for (regno = 0; regno < _jitc->reglen; regno++) {
|
||||||
if ((jit_class(_rvs[regno].spec) & spec) == spec &&
|
if ((jit_class(_rvs[regno].spec) & spec) == spec &&
|
||||||
!jit_regset_tstbit(_jitc->regarg, regno) &&
|
!jit_regset_tstbit(&_jitc->regarg, regno) &&
|
||||||
!jit_regset_tstbit(_jitc->reglive, regno))
|
!jit_regset_tstbit(&_jitc->reglive, regno))
|
||||||
goto regarg;
|
goto regarg;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -213,8 +213,8 @@ _jit_get_reg(jit_state_t *_jit, jit_int32_t regspec)
|
||||||
* for the current instruction */
|
* for the current instruction */
|
||||||
for (regno = 0; regno < _jitc->reglen; regno++) {
|
for (regno = 0; regno < _jitc->reglen; regno++) {
|
||||||
if ((jit_class(_rvs[regno].spec) & spec) == spec &&
|
if ((jit_class(_rvs[regno].spec) & spec) == spec &&
|
||||||
!jit_regset_tstbit(_jitc->regsav, regno) &&
|
!jit_regset_tstbit(&_jitc->regsav, regno) &&
|
||||||
!jit_regset_tstbit(_jitc->regarg, regno) &&
|
!jit_regset_tstbit(&_jitc->regarg, regno) &&
|
||||||
!(regspec & jit_class_nospill)) {
|
!(regspec & jit_class_nospill)) {
|
||||||
spill:
|
spill:
|
||||||
assert(_jitc->function);
|
assert(_jitc->function);
|
||||||
|
@ -234,15 +234,15 @@ _jit_get_reg(jit_state_t *_jit, jit_int32_t regspec)
|
||||||
}
|
}
|
||||||
emit_stxi_d(_jitc->function->regoff[regno], JIT_FP, regno);
|
emit_stxi_d(_jitc->function->regoff[regno], JIT_FP, regno);
|
||||||
}
|
}
|
||||||
jit_regset_setbit(_jitc->regsav, regno);
|
jit_regset_setbit(&_jitc->regsav, regno);
|
||||||
regarg:
|
regarg:
|
||||||
jit_regset_setbit(_jitc->regarg, regno);
|
jit_regset_setbit(&_jitc->regarg, regno);
|
||||||
if (jit_class(_rvs[regno].spec) & jit_class_sav) {
|
if (jit_class(_rvs[regno].spec) & jit_class_sav) {
|
||||||
/* if will modify callee save registers without a
|
/* if will modify callee save registers without a
|
||||||
* function prolog, better patch this assertion */
|
* function prolog, better patch this assertion */
|
||||||
assert(_jitc->function);
|
assert(_jitc->function);
|
||||||
if (!jit_regset_tstbit(_jitc->function->regset, regno)) {
|
if (!jit_regset_tstbit(&_jitc->function->regset, regno)) {
|
||||||
jit_regset_setbit(_jitc->function->regset, regno);
|
jit_regset_setbit(&_jitc->function->regset, regno);
|
||||||
_jitc->again = 1;
|
_jitc->again = 1;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -255,10 +255,10 @@ _jit_get_reg(jit_state_t *_jit, jit_int32_t regspec)
|
||||||
assert(!(regspec & jit_class_nospill));
|
assert(!(regspec & jit_class_nospill));
|
||||||
for (regno = 0; regno < _jitc->reglen; regno++) {
|
for (regno = 0; regno < _jitc->reglen; regno++) {
|
||||||
if ((jit_class(_rvs[regno].spec) & spec) == spec &&
|
if ((jit_class(_rvs[regno].spec) & spec) == spec &&
|
||||||
!jit_regset_tstbit(_jitc->regsav, regno) &&
|
!jit_regset_tstbit(&_jitc->regsav, regno) &&
|
||||||
!jit_regset_tstbit(_jitc->regarg, regno)) {
|
!jit_regset_tstbit(&_jitc->regarg, regno)) {
|
||||||
jit_regset_setbit(_jitc->regarg, regno);
|
jit_regset_setbit(&_jitc->regarg, regno);
|
||||||
jit_regset_setbit(_jitc->regsav, regno);
|
jit_regset_setbit(&_jitc->regsav, regno);
|
||||||
jit_save(regno);
|
jit_save(regno);
|
||||||
return (jit_regno_patch|regno);
|
return (jit_regno_patch|regno);
|
||||||
}
|
}
|
||||||
|
@ -275,7 +275,7 @@ void
|
||||||
_jit_unget_reg(jit_state_t *_jit, jit_int32_t regno)
|
_jit_unget_reg(jit_state_t *_jit, jit_int32_t regno)
|
||||||
{
|
{
|
||||||
regno = jit_regno(regno);
|
regno = jit_regno(regno);
|
||||||
if (jit_regset_tstbit(_jitc->regsav, regno)) {
|
if (jit_regset_tstbit(&_jitc->regsav, regno)) {
|
||||||
if (_jitc->emit) {
|
if (_jitc->emit) {
|
||||||
if (jit_class(_rvs[regno].spec) & jit_class_gpr)
|
if (jit_class(_rvs[regno].spec) & jit_class_gpr)
|
||||||
emit_ldxi(regno, JIT_FP, _jitc->function->regoff[regno]);
|
emit_ldxi(regno, JIT_FP, _jitc->function->regoff[regno]);
|
||||||
|
@ -284,18 +284,18 @@ _jit_unget_reg(jit_state_t *_jit, jit_int32_t regno)
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
jit_load(regno);
|
jit_load(regno);
|
||||||
jit_regset_clrbit(_jitc->regsav, regno);
|
jit_regset_clrbit(&_jitc->regsav, regno);
|
||||||
}
|
}
|
||||||
assert(jit_regset_tstbit(_jitc->regarg, regno));
|
assert(jit_regset_tstbit(&_jitc->regarg, regno));
|
||||||
jit_regset_clrbit(_jitc->regarg, regno);
|
jit_regset_clrbit(&_jitc->regarg, regno);
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned long
|
unsigned long
|
||||||
jit_regset_scan1(jit_regset_t set, jit_int32_t offset)
|
jit_regset_scan1(jit_regset_t *set, jit_int32_t offset)
|
||||||
{
|
{
|
||||||
assert(offset >= 0 && offset <= 63);
|
assert(offset >= 0 && offset <= 63);
|
||||||
for (; offset < 64; offset++) {
|
for (; offset < 64; offset++) {
|
||||||
if (set & (1LL << offset))
|
if (*set & (1LL << offset))
|
||||||
return (offset);
|
return (offset);
|
||||||
}
|
}
|
||||||
return (ULONG_MAX);
|
return (ULONG_MAX);
|
||||||
|
@ -508,8 +508,8 @@ _del_label(jit_state_t *_jit, jit_node_t *prev, jit_node_t *node)
|
||||||
|
|
||||||
/* del_label() should only be called when optimizing.
|
/* del_label() should only be called when optimizing.
|
||||||
* This will leave an empty block index */
|
* This will leave an empty block index */
|
||||||
jit_regset_del(block->reglive);
|
jit_regset_del(&block->reglive);
|
||||||
jit_regset_del(block->regmask);
|
jit_regset_del(&block->regmask);
|
||||||
block->label = NULL;
|
block->label = NULL;
|
||||||
|
|
||||||
/* redundant, should be already true */
|
/* redundant, should be already true */
|
||||||
|
@ -579,10 +579,10 @@ jit_new_state(void)
|
||||||
|
|
||||||
jit_alloc((jit_pointer_t *)&_jit, sizeof(jit_state_t));
|
jit_alloc((jit_pointer_t *)&_jit, sizeof(jit_state_t));
|
||||||
jit_alloc((jit_pointer_t *)&_jitc, sizeof(jit_compiler_t));
|
jit_alloc((jit_pointer_t *)&_jitc, sizeof(jit_compiler_t));
|
||||||
jit_regset_new(_jitc->regarg);
|
jit_regset_new(&_jitc->regarg);
|
||||||
jit_regset_new(_jitc->regsav);
|
jit_regset_new(&_jitc->regsav);
|
||||||
jit_regset_new(_jitc->reglive);
|
jit_regset_new(&_jitc->reglive);
|
||||||
jit_regset_new(_jitc->regmask);
|
jit_regset_new(&_jitc->regmask);
|
||||||
bmp_init();
|
bmp_init();
|
||||||
|
|
||||||
jit_init();
|
jit_init();
|
||||||
|
@ -891,8 +891,8 @@ _jit_link(jit_state_t *_jit, jit_node_t *node)
|
||||||
block = _jitc->blocks.ptr + _jitc->blocks.offset;
|
block = _jitc->blocks.ptr + _jitc->blocks.offset;
|
||||||
block->label = node;
|
block->label = node;
|
||||||
node->v.w = _jitc->blocks.offset;
|
node->v.w = _jitc->blocks.offset;
|
||||||
jit_regset_new(block->reglive);
|
jit_regset_new(&block->reglive);
|
||||||
jit_regset_new(block->regmask);
|
jit_regset_new(&block->regmask);
|
||||||
++_jitc->blocks.offset;
|
++_jitc->blocks.offset;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1216,7 +1216,7 @@ _jit_optimize(jit_state_t *_jit)
|
||||||
if (!block->label)
|
if (!block->label)
|
||||||
continue;
|
continue;
|
||||||
if (block->label->code != jit_code_epilog) {
|
if (block->label->code != jit_code_epilog) {
|
||||||
jit_regset_set(_jitc->regmask, block->regmask);
|
jit_regset_set(&_jitc->regmask, &block->regmask);
|
||||||
jit_update(block->label->next, &block->reglive, &_jitc->regmask);
|
jit_update(block->label->next, &block->reglive, &_jitc->regmask);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -1283,11 +1283,11 @@ _jit_optimize(jit_state_t *_jit)
|
||||||
if (_jitc->function) {
|
if (_jitc->function) {
|
||||||
if ((mask & (jit_cc_a0_reg|jit_cc_a0_chg)) ==
|
if ((mask & (jit_cc_a0_reg|jit_cc_a0_chg)) ==
|
||||||
(jit_cc_a0_reg|jit_cc_a0_chg))
|
(jit_cc_a0_reg|jit_cc_a0_chg))
|
||||||
jit_regset_setbit(_jitc->function->regset,
|
jit_regset_setbit(&_jitc->function->regset,
|
||||||
jit_regno(node->u.w));
|
jit_regno(node->u.w));
|
||||||
if ((mask & (jit_cc_a1_reg|jit_cc_a1_chg)) ==
|
if ((mask & (jit_cc_a1_reg|jit_cc_a1_chg)) ==
|
||||||
(jit_cc_a1_reg|jit_cc_a1_chg))
|
(jit_cc_a1_reg|jit_cc_a1_chg))
|
||||||
jit_regset_setbit(_jitc->function->regset,
|
jit_regset_setbit(&_jitc->function->regset,
|
||||||
jit_regno(node->v.w));
|
jit_regno(node->v.w));
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
@ -1331,34 +1331,34 @@ _jit_reglive(jit_state_t *_jit, jit_node_t *node)
|
||||||
switch (node->code) {
|
switch (node->code) {
|
||||||
case jit_code_label: case jit_code_prolog: case jit_code_epilog:
|
case jit_code_label: case jit_code_prolog: case jit_code_epilog:
|
||||||
block = _jitc->blocks.ptr + node->v.w;
|
block = _jitc->blocks.ptr + node->v.w;
|
||||||
jit_regset_set(_jitc->reglive, block->reglive);
|
jit_regset_set(&_jitc->reglive, &block->reglive);
|
||||||
break;
|
break;
|
||||||
case jit_code_callr:
|
case jit_code_callr:
|
||||||
value = jit_regno(node->u.w);
|
value = jit_regno(node->u.w);
|
||||||
if (!(node->u.w & jit_regno_patch)) {
|
if (!(node->u.w & jit_regno_patch)) {
|
||||||
jit_regset_setbit(_jitc->reglive, value);
|
jit_regset_setbit(&_jitc->reglive, value);
|
||||||
}
|
}
|
||||||
case jit_code_calli:
|
case jit_code_calli:
|
||||||
for (value = 0; value < _jitc->reglen; value++) {
|
for (value = 0; value < _jitc->reglen; value++) {
|
||||||
spec = jit_class(_rvs[value].spec);
|
spec = jit_class(_rvs[value].spec);
|
||||||
if ((spec & jit_class_arg) && jit_regarg_p(node, value))
|
if ((spec & jit_class_arg) && jit_regarg_p(node, value))
|
||||||
jit_regset_setbit(_jitc->reglive, value);
|
jit_regset_setbit(&_jitc->reglive, value);
|
||||||
else if (!(spec & jit_class_sav))
|
else if (!(spec & jit_class_sav))
|
||||||
jit_regset_clrbit(_jitc->reglive, value);
|
jit_regset_clrbit(&_jitc->reglive, value);
|
||||||
}
|
}
|
||||||
#if defined(JIT_RET)
|
#if defined(JIT_RET)
|
||||||
/* Explicitly set return registers as live, because retval
|
/* Explicitly set return registers as live, because retval
|
||||||
* should be free to not create a note, and/or user not
|
* should be free to not create a note, and/or user not
|
||||||
* call jit_retval (but not a good idea to expect JIT_R0
|
* call jit_retval (but not a good idea to expect JIT_R0
|
||||||
* to match JIT_RET) */
|
* to match JIT_RET) */
|
||||||
jit_regset_setbit(_jitc->reglive, JIT_RET);
|
jit_regset_setbit(&_jitc->reglive, JIT_RET);
|
||||||
# if __arm__
|
# if __arm__
|
||||||
/* FIXME need a better logic (and r2-r3 may contain results) */
|
/* FIXME need a better logic (and r2-r3 may contain results) */
|
||||||
jit_regset_setbit(_jitc->reglive, _R1);
|
jit_regset_setbit(&_jitc->reglive, _R1);
|
||||||
# endif
|
# endif
|
||||||
#endif
|
#endif
|
||||||
#if defined(JIT_FRET)
|
#if defined(JIT_FRET)
|
||||||
jit_regset_setbit(_jitc->reglive, JIT_FRET);
|
jit_regset_setbit(&_jitc->reglive, JIT_FRET);
|
||||||
#endif
|
#endif
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
|
@ -1367,49 +1367,50 @@ _jit_reglive(jit_state_t *_jit, jit_node_t *node)
|
||||||
if (value & jit_cc_a0_rlh) {
|
if (value & jit_cc_a0_rlh) {
|
||||||
if (!(node->u.q.l & jit_regno_patch)) {
|
if (!(node->u.q.l & jit_regno_patch)) {
|
||||||
if (value & jit_cc_a0_chg) {
|
if (value & jit_cc_a0_chg) {
|
||||||
jit_regset_clrbit(_jitc->reglive, node->u.q.l);
|
jit_regset_clrbit(&_jitc->reglive, node->u.q.l);
|
||||||
jit_regset_setbit(_jitc->regmask, node->u.q.l);
|
jit_regset_setbit(&_jitc->regmask, node->u.q.l);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
jit_regset_setbit(_jitc->reglive, node->u.q.l);
|
jit_regset_setbit(&_jitc->reglive, node->u.q.l);
|
||||||
}
|
}
|
||||||
if (!(node->u.q.h & jit_regno_patch)) {
|
if (!(node->u.q.h & jit_regno_patch)) {
|
||||||
if (value & jit_cc_a0_chg) {
|
if (value & jit_cc_a0_chg) {
|
||||||
jit_regset_clrbit(_jitc->reglive, node->u.q.h);
|
jit_regset_clrbit(&_jitc->reglive, node->u.q.h);
|
||||||
jit_regset_setbit(_jitc->regmask, node->u.q.h);
|
jit_regset_setbit(&_jitc->regmask, node->u.q.h);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
jit_regset_setbit(_jitc->reglive, node->u.q.h);
|
jit_regset_setbit(&_jitc->reglive, node->u.q.h);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
if (!(node->u.w & jit_regno_patch)) {
|
if (!(node->u.w & jit_regno_patch)) {
|
||||||
if (value & jit_cc_a0_chg) {
|
if (value & jit_cc_a0_chg) {
|
||||||
jit_regset_clrbit(_jitc->reglive, node->u.w);
|
jit_regset_clrbit(&_jitc->reglive, node->u.w);
|
||||||
jit_regset_setbit(_jitc->regmask, node->u.w);
|
jit_regset_setbit(&_jitc->regmask, node->u.w);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
jit_regset_setbit(_jitc->reglive, node->u.w);
|
jit_regset_setbit(&_jitc->reglive, node->u.w);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if ((value & jit_cc_a1_reg) && !(node->v.w & jit_regno_patch)) {
|
if ((value & jit_cc_a1_reg) && !(node->v.w & jit_regno_patch)) {
|
||||||
if (value & jit_cc_a1_chg) {
|
if (value & jit_cc_a1_chg) {
|
||||||
jit_regset_clrbit(_jitc->reglive, node->v.w);
|
jit_regset_clrbit(&_jitc->reglive, node->v.w);
|
||||||
jit_regset_setbit(_jitc->regmask, node->v.w);
|
jit_regset_setbit(&_jitc->regmask, node->v.w);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
jit_regset_setbit(_jitc->reglive, node->v.w);
|
jit_regset_setbit(&_jitc->reglive, node->v.w);
|
||||||
}
|
}
|
||||||
if ((value & jit_cc_a2_reg) && !(node->w.w & jit_regno_patch))
|
if ((value & jit_cc_a2_reg) && !(node->w.w & jit_regno_patch))
|
||||||
jit_regset_setbit(_jitc->reglive, node->w.w);
|
jit_regset_setbit(&_jitc->reglive, node->w.w);
|
||||||
if (jit_regset_set_p(_jitc->regmask)) {
|
if (jit_regset_set_p(&_jitc->regmask)) {
|
||||||
bmp_zero();
|
bmp_zero();
|
||||||
jit_update(node->next, &_jitc->reglive, &_jitc->regmask);
|
jit_update(node->next, &_jitc->reglive, &_jitc->regmask);
|
||||||
if (jit_regset_set_p(_jitc->regmask)) {
|
if (jit_regset_set_p(&_jitc->regmask)) {
|
||||||
/* any unresolved live state is considered as live */
|
/* any unresolved live state is considered as live */
|
||||||
jit_regset_ior(_jitc->reglive, _jitc->reglive, _jitc->regmask);
|
jit_regset_ior(&_jitc->reglive,
|
||||||
jit_regset_set_ui(_jitc->regmask, 0);
|
&_jitc->reglive, &_jitc->regmask);
|
||||||
|
jit_regset_set_ui(&_jitc->regmask, 0);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
@ -1421,16 +1422,16 @@ _jit_regarg_set(jit_state_t *_jit, jit_node_t *node, jit_int32_t value)
|
||||||
{
|
{
|
||||||
if (value & jit_cc_a0_reg) {
|
if (value & jit_cc_a0_reg) {
|
||||||
if (value & jit_cc_a0_rlh) {
|
if (value & jit_cc_a0_rlh) {
|
||||||
jit_regset_setbit(_jitc->regarg, jit_regno(node->u.q.l));
|
jit_regset_setbit(&_jitc->regarg, jit_regno(node->u.q.l));
|
||||||
jit_regset_setbit(_jitc->regarg, jit_regno(node->u.q.h));
|
jit_regset_setbit(&_jitc->regarg, jit_regno(node->u.q.h));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
jit_regset_setbit(_jitc->regarg, jit_regno(node->u.w));
|
jit_regset_setbit(&_jitc->regarg, jit_regno(node->u.w));
|
||||||
}
|
}
|
||||||
if (value & jit_cc_a1_reg)
|
if (value & jit_cc_a1_reg)
|
||||||
jit_regset_setbit(_jitc->regarg, jit_regno(node->v.w));
|
jit_regset_setbit(&_jitc->regarg, jit_regno(node->v.w));
|
||||||
if (value & jit_cc_a2_reg)
|
if (value & jit_cc_a2_reg)
|
||||||
jit_regset_setbit(_jitc->regarg, jit_regno(node->w.w));
|
jit_regset_setbit(&_jitc->regarg, jit_regno(node->w.w));
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
@ -1438,16 +1439,16 @@ _jit_regarg_clr(jit_state_t *_jit, jit_node_t *node, jit_int32_t value)
|
||||||
{
|
{
|
||||||
if (value & jit_cc_a0_reg) {
|
if (value & jit_cc_a0_reg) {
|
||||||
if (value & jit_cc_a0_rlh) {
|
if (value & jit_cc_a0_rlh) {
|
||||||
jit_regset_clrbit(_jitc->regarg, jit_regno(node->u.q.l));
|
jit_regset_clrbit(&_jitc->regarg, jit_regno(node->u.q.l));
|
||||||
jit_regset_clrbit(_jitc->regarg, jit_regno(node->u.q.h));
|
jit_regset_clrbit(&_jitc->regarg, jit_regno(node->u.q.h));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
jit_regset_clrbit(_jitc->regarg, jit_regno(node->u.w));
|
jit_regset_clrbit(&_jitc->regarg, jit_regno(node->u.w));
|
||||||
}
|
}
|
||||||
if (value & jit_cc_a1_reg)
|
if (value & jit_cc_a1_reg)
|
||||||
jit_regset_clrbit(_jitc->regarg, jit_regno(node->v.w));
|
jit_regset_clrbit(&_jitc->regarg, jit_regno(node->v.w));
|
||||||
if (value & jit_cc_a2_reg)
|
if (value & jit_cc_a2_reg)
|
||||||
jit_regset_clrbit(_jitc->regarg, jit_regno(node->w.w));
|
jit_regset_clrbit(&_jitc->regarg, jit_regno(node->w.w));
|
||||||
}
|
}
|
||||||
|
|
||||||
jit_pointer_t
|
jit_pointer_t
|
||||||
|
@ -1536,7 +1537,7 @@ _jit_setup(jit_state_t *_jit, jit_block_t *block)
|
||||||
unsigned long value;
|
unsigned long value;
|
||||||
|
|
||||||
jump = 0;
|
jump = 0;
|
||||||
jit_regset_set_ui(regmask, (1LL << _jitc->reglen) - 1);
|
jit_regset_set_mask(®mask, _jitc->reglen);
|
||||||
for (node = block->label->next; node; node = node->next) {
|
for (node = block->label->next; node; node = node->next) {
|
||||||
switch (node->code) {
|
switch (node->code) {
|
||||||
case jit_code_label: case jit_code_prolog:
|
case jit_code_label: case jit_code_prolog:
|
||||||
|
@ -1548,44 +1549,44 @@ _jit_setup(jit_state_t *_jit, jit_block_t *block)
|
||||||
live = !(value & jit_cc_a0_chg);
|
live = !(value & jit_cc_a0_chg);
|
||||||
if (value & jit_cc_a0_rlh) {
|
if (value & jit_cc_a0_rlh) {
|
||||||
if (!(node->u.q.l & jit_regno_patch) &&
|
if (!(node->u.q.l & jit_regno_patch) &&
|
||||||
jit_regset_tstbit(regmask, node->u.q.l)) {
|
jit_regset_tstbit(®mask, node->u.q.l)) {
|
||||||
if (live || !jump)
|
if (live || !jump)
|
||||||
jit_regset_clrbit(regmask, node->u.q.l);
|
jit_regset_clrbit(®mask, node->u.q.l);
|
||||||
if (live)
|
if (live)
|
||||||
jit_regset_setbit(reglive, node->u.q.l);
|
jit_regset_setbit(®live, node->u.q.l);
|
||||||
}
|
}
|
||||||
if (!(node->u.q.h & jit_regno_patch) &&
|
if (!(node->u.q.h & jit_regno_patch) &&
|
||||||
jit_regset_tstbit(regmask, node->u.q.h)) {
|
jit_regset_tstbit(®mask, node->u.q.h)) {
|
||||||
if (live || !jump)
|
if (live || !jump)
|
||||||
jit_regset_clrbit(regmask, node->u.q.h);
|
jit_regset_clrbit(®mask, node->u.q.h);
|
||||||
if (live)
|
if (live)
|
||||||
jit_regset_setbit(reglive, node->u.q.h);
|
jit_regset_setbit(®live, node->u.q.h);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
if (!(node->u.w & jit_regno_patch) &&
|
if (!(node->u.w & jit_regno_patch) &&
|
||||||
jit_regset_tstbit(regmask, node->u.w)) {
|
jit_regset_tstbit(®mask, node->u.w)) {
|
||||||
if (live || !jump)
|
if (live || !jump)
|
||||||
jit_regset_clrbit(regmask, node->u.w);
|
jit_regset_clrbit(®mask, node->u.w);
|
||||||
if (live)
|
if (live)
|
||||||
jit_regset_setbit(reglive, node->u.w);
|
jit_regset_setbit(®live, node->u.w);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if ((value & jit_cc_a1_reg) &&
|
if ((value & jit_cc_a1_reg) &&
|
||||||
!(node->v.w & jit_regno_patch) &&
|
!(node->v.w & jit_regno_patch) &&
|
||||||
jit_regset_tstbit(regmask, node->v.w)) {
|
jit_regset_tstbit(®mask, node->v.w)) {
|
||||||
live = !(value & jit_cc_a1_chg);
|
live = !(value & jit_cc_a1_chg);
|
||||||
if (live || !jump)
|
if (live || !jump)
|
||||||
jit_regset_clrbit(regmask, node->v.w);
|
jit_regset_clrbit(®mask, node->v.w);
|
||||||
if (live)
|
if (live)
|
||||||
jit_regset_setbit(reglive, node->v.w);
|
jit_regset_setbit(®live, node->v.w);
|
||||||
}
|
}
|
||||||
if ((value & jit_cc_a2_reg) &&
|
if ((value & jit_cc_a2_reg) &&
|
||||||
!(node->w.w & jit_regno_patch) &&
|
!(node->w.w & jit_regno_patch) &&
|
||||||
jit_regset_tstbit(regmask, node->w.w)) {
|
jit_regset_tstbit(®mask, node->w.w)) {
|
||||||
jit_regset_clrbit(regmask, node->w.w);
|
jit_regset_clrbit(®mask, node->w.w);
|
||||||
jit_regset_setbit(reglive, node->w.w);
|
jit_regset_setbit(®live, node->w.w);
|
||||||
}
|
}
|
||||||
if (value & jit_cc_a0_jmp)
|
if (value & jit_cc_a0_jmp)
|
||||||
jump = 1;
|
jump = 1;
|
||||||
|
@ -1615,7 +1616,7 @@ _jit_update(jit_state_t *_jit, jit_node_t *node,
|
||||||
|
|
||||||
for (; node; node = node->next) {
|
for (; node; node = node->next) {
|
||||||
restart:
|
restart:
|
||||||
if (jit_regset_set_p(*mask) == 0)
|
if (jit_regset_set_p(mask) == 0)
|
||||||
break;
|
break;
|
||||||
switch (node->code) {
|
switch (node->code) {
|
||||||
case jit_code_label:
|
case jit_code_label:
|
||||||
|
@ -1623,96 +1624,96 @@ _jit_update(jit_state_t *_jit, jit_node_t *node,
|
||||||
if (bmp_tst(node->v.w))
|
if (bmp_tst(node->v.w))
|
||||||
return;
|
return;
|
||||||
bmp_set(node->v.w);
|
bmp_set(node->v.w);
|
||||||
jit_regset_and(ztmp, *mask, block->reglive);
|
jit_regset_and(&ztmp, mask, &block->reglive);
|
||||||
if (jit_regset_set_p(ztmp)) {
|
if (jit_regset_set_p(&ztmp)) {
|
||||||
jit_regset_ior(*live, *live, ztmp);
|
jit_regset_ior(live, live, &ztmp);
|
||||||
jit_regset_com(ztmp, ztmp);
|
jit_regset_com(&ztmp, &ztmp);
|
||||||
jit_regset_and(*mask, *mask, ztmp);
|
jit_regset_and(mask, mask, &ztmp);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case jit_code_prolog: case jit_code_epilog:
|
case jit_code_prolog: case jit_code_epilog:
|
||||||
jit_regset_set_ui(*mask, 0);
|
jit_regset_set_ui(mask, 0);
|
||||||
return;
|
return;
|
||||||
case jit_code_callr:
|
case jit_code_callr:
|
||||||
value = jit_regno(node->u.w);
|
value = jit_regno(node->u.w);
|
||||||
if (!(node->u.w & jit_regno_patch)) {
|
if (!(node->u.w & jit_regno_patch)) {
|
||||||
if (jit_regset_tstbit(*mask, value)) {
|
if (jit_regset_tstbit(mask, value)) {
|
||||||
jit_regset_clrbit(*mask, value);
|
jit_regset_clrbit(mask, value);
|
||||||
jit_regset_setbit(*live, value);
|
jit_regset_setbit(live, value);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
case jit_code_calli:
|
case jit_code_calli:
|
||||||
#if defined(JIT_RET)
|
#if defined(JIT_RET)
|
||||||
if (jit_regset_tstbit(*mask, JIT_RET)) {
|
if (jit_regset_tstbit(mask, JIT_RET)) {
|
||||||
jit_regset_setbit(_jitc->reglive, JIT_RET);
|
jit_regset_setbit(&_jitc->reglive, JIT_RET);
|
||||||
jit_regset_clrbit(*mask, JIT_RET);
|
jit_regset_clrbit(mask, JIT_RET);
|
||||||
}
|
}
|
||||||
# if __arm__
|
# if __arm__
|
||||||
if (jit_regset_tstbit(*mask, _R1)) {
|
if (jit_regset_tstbit(mask, _R1)) {
|
||||||
jit_regset_setbit(_jitc->reglive, _R1);
|
jit_regset_setbit(&_jitc->reglive, _R1);
|
||||||
jit_regset_clrbit(*mask, _R1);
|
jit_regset_clrbit(mask, _R1);
|
||||||
}
|
}
|
||||||
# endif
|
# endif
|
||||||
#endif
|
#endif
|
||||||
#if defined(JIT_FRET)
|
#if defined(JIT_FRET)
|
||||||
if (jit_regset_tstbit(*mask, JIT_FRET)) {
|
if (jit_regset_tstbit(mask, JIT_FRET)) {
|
||||||
jit_regset_setbit(_jitc->reglive, JIT_FRET);
|
jit_regset_setbit(&_jitc->reglive, JIT_FRET);
|
||||||
jit_regset_clrbit(*mask, JIT_FRET);
|
jit_regset_clrbit(mask, JIT_FRET);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
for (value = 0; value < _jitc->reglen; ++value) {
|
for (value = 0; value < _jitc->reglen; ++value) {
|
||||||
value = jit_regset_scan1(*mask, value);
|
value = jit_regset_scan1(mask, value);
|
||||||
if (value >= _jitc->reglen)
|
if (value >= _jitc->reglen)
|
||||||
break;
|
break;
|
||||||
spec = jit_class(_rvs[value].spec);
|
spec = jit_class(_rvs[value].spec);
|
||||||
if (!(spec & jit_class_sav))
|
if (!(spec & jit_class_sav))
|
||||||
jit_regset_clrbit(*mask, value);
|
jit_regset_clrbit(mask, value);
|
||||||
if ((spec & jit_class_arg) && jit_regarg_p(node, value))
|
if ((spec & jit_class_arg) && jit_regarg_p(node, value))
|
||||||
jit_regset_setbit(*live, value);
|
jit_regset_setbit(live, value);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
value = jit_classify(node->code);
|
value = jit_classify(node->code);
|
||||||
if (value & jit_cc_a2_reg) {
|
if (value & jit_cc_a2_reg) {
|
||||||
if (!(node->w.w & jit_regno_patch)) {
|
if (!(node->w.w & jit_regno_patch)) {
|
||||||
if (jit_regset_tstbit(*mask, node->w.w)) {
|
if (jit_regset_tstbit(mask, node->w.w)) {
|
||||||
jit_regset_clrbit(*mask, node->w.w);
|
jit_regset_clrbit(mask, node->w.w);
|
||||||
jit_regset_setbit(*live, node->w.w);
|
jit_regset_setbit(live, node->w.w);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (value & jit_cc_a1_reg) {
|
if (value & jit_cc_a1_reg) {
|
||||||
if (!(node->v.w & jit_regno_patch)) {
|
if (!(node->v.w & jit_regno_patch)) {
|
||||||
if (jit_regset_tstbit(*mask, node->v.w)) {
|
if (jit_regset_tstbit(mask, node->v.w)) {
|
||||||
jit_regset_clrbit(*mask, node->v.w);
|
jit_regset_clrbit(mask, node->v.w);
|
||||||
if (!(value & jit_cc_a1_chg))
|
if (!(value & jit_cc_a1_chg))
|
||||||
jit_regset_setbit(*live, node->v.w);
|
jit_regset_setbit(live, node->v.w);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (value & jit_cc_a0_reg) {
|
if (value & jit_cc_a0_reg) {
|
||||||
if (value & jit_cc_a0_rlh) {
|
if (value & jit_cc_a0_rlh) {
|
||||||
if (!(node->u.q.l & jit_regno_patch)) {
|
if (!(node->u.q.l & jit_regno_patch)) {
|
||||||
if (jit_regset_tstbit(*mask, node->u.q.l)) {
|
if (jit_regset_tstbit(mask, node->u.q.l)) {
|
||||||
jit_regset_clrbit(*mask, node->u.q.l);
|
jit_regset_clrbit(mask, node->u.q.l);
|
||||||
if (!(value & jit_cc_a0_chg))
|
if (!(value & jit_cc_a0_chg))
|
||||||
jit_regset_setbit(*live, node->u.q.l);
|
jit_regset_setbit(live, node->u.q.l);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (!(node->u.q.h & jit_regno_patch)) {
|
if (!(node->u.q.h & jit_regno_patch)) {
|
||||||
if (jit_regset_tstbit(*mask, node->u.q.h)) {
|
if (jit_regset_tstbit(mask, node->u.q.h)) {
|
||||||
jit_regset_clrbit(*mask, node->u.q.h);
|
jit_regset_clrbit(mask, node->u.q.h);
|
||||||
if (!(value & jit_cc_a0_chg))
|
if (!(value & jit_cc_a0_chg))
|
||||||
jit_regset_setbit(*live, node->u.q.h);
|
jit_regset_setbit(live, node->u.q.h);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
if (!(node->u.w & jit_regno_patch)) {
|
if (!(node->u.w & jit_regno_patch)) {
|
||||||
if (jit_regset_tstbit(*mask, node->u.w)) {
|
if (jit_regset_tstbit(mask, node->u.w)) {
|
||||||
jit_regset_clrbit(*mask, node->u.w);
|
jit_regset_clrbit(mask, node->u.w);
|
||||||
if (!(value & jit_cc_a0_chg))
|
if (!(value & jit_cc_a0_chg))
|
||||||
jit_regset_setbit(*live, node->u.w);
|
jit_regset_setbit(live, node->u.w);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -1728,29 +1729,29 @@ _jit_update(jit_state_t *_jit, jit_node_t *node,
|
||||||
if (bmp_tst(label->v.w))
|
if (bmp_tst(label->v.w))
|
||||||
continue;
|
continue;
|
||||||
bmp_set(label->v.w);
|
bmp_set(label->v.w);
|
||||||
jit_regset_and(ztmp, *mask, block->reglive);
|
jit_regset_and(&ztmp, mask, &block->reglive);
|
||||||
if (jit_regset_set_p(ztmp)) {
|
if (jit_regset_set_p(&ztmp)) {
|
||||||
jit_regset_ior(*live, *live, ztmp);
|
jit_regset_ior(live, live, &ztmp);
|
||||||
jit_regset_com(ztmp, ztmp);
|
jit_regset_com(&ztmp, &ztmp);
|
||||||
jit_regset_and(*mask, *mask, ztmp);
|
jit_regset_and(mask, mask, &ztmp);
|
||||||
}
|
}
|
||||||
if (jit_regset_set_p(*mask) == 0)
|
if (jit_regset_set_p(mask) == 0)
|
||||||
return;
|
return;
|
||||||
/* restore mask if branch is conditional */
|
/* restore mask if branch is conditional */
|
||||||
zmask = *mask;
|
jit_regset_set(&zmask, mask);
|
||||||
jit_update(block->label->next, live, &zmask);
|
jit_update(block->label->next, live, &zmask);
|
||||||
jit_regset_xor(ztmp, zmask, *mask);
|
jit_regset_xor(&ztmp, &zmask, mask);
|
||||||
/* remove known live registers from mask */
|
/* remove known live registers from mask */
|
||||||
if (jit_regset_set_p(ztmp)) {
|
if (jit_regset_set_p(&ztmp)) {
|
||||||
jit_regset_and(ztmp, ztmp, *live);
|
jit_regset_and(&ztmp, &ztmp, live);
|
||||||
jit_regset_com(ztmp, ztmp);
|
jit_regset_com(&ztmp, &ztmp);
|
||||||
jit_regset_and(*mask, *mask, ztmp);
|
jit_regset_and(mask, mask, &ztmp);
|
||||||
}
|
}
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
/* assume value is live due to jump to unknown location */
|
/* assume value is live due to jump to unknown location */
|
||||||
jit_regset_ior(*live, *live, *mask);
|
jit_regset_ior(live, live, mask);
|
||||||
jit_regset_set_ui(*mask, 0);
|
jit_regset_set_ui(mask, 0);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
@ -2519,11 +2520,11 @@ _register_change_p(jit_state_t *_jit, jit_node_t *node, jit_node_t *link,
|
||||||
static jit_bool_t
|
static jit_bool_t
|
||||||
_spill_reglive_p(jit_state_t *_jit, jit_node_t *node, jit_int32_t regno)
|
_spill_reglive_p(jit_state_t *_jit, jit_node_t *node, jit_int32_t regno)
|
||||||
{
|
{
|
||||||
if (!jit_regset_tstbit(_jitc->reglive, regno)) {
|
if (!jit_regset_tstbit(&_jitc->reglive, regno)) {
|
||||||
bmp_zero();
|
bmp_zero();
|
||||||
jit_regset_setbit(_jitc->regmask, regno);
|
jit_regset_setbit(&_jitc->regmask, regno);
|
||||||
jit_update(node->next, &_jitc->reglive, &_jitc->regmask);
|
jit_update(node->next, &_jitc->reglive, &_jitc->regmask);
|
||||||
if (!jit_regset_tstbit(_jitc->reglive, regno) &&
|
if (!jit_regset_tstbit(&_jitc->reglive, regno) &&
|
||||||
register_change_p(node->next, node->link, regno) != jit_reg_change)
|
register_change_p(node->next, node->link, regno) != jit_reg_change)
|
||||||
return (0);
|
return (0);
|
||||||
}
|
}
|
||||||
|
@ -2568,7 +2569,7 @@ _patch_registers(jit_state_t *_jit)
|
||||||
if (value != regno &&
|
if (value != regno &&
|
||||||
((jit_class(_rvs[value].spec) & spec) &
|
((jit_class(_rvs[value].spec) & spec) &
|
||||||
~jit_class_arg) == spec &&
|
~jit_class_arg) == spec &&
|
||||||
!jit_regset_tstbit(_jitc->regarg, value) &&
|
!jit_regset_tstbit(&_jitc->regarg, value) &&
|
||||||
!spill_reglive_p(node, value))
|
!spill_reglive_p(node, value))
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -2580,7 +2581,7 @@ _patch_registers(jit_state_t *_jit)
|
||||||
/* mark as live just in case there are nested
|
/* mark as live just in case there are nested
|
||||||
* register patches, so that next patch will
|
* register patches, so that next patch will
|
||||||
* not want to use the same register */
|
* not want to use the same register */
|
||||||
jit_regset_setbit(_jitc->reglive, value);
|
jit_regset_setbit(&_jitc->reglive, value);
|
||||||
/* register is not live, just remove spill/reload */
|
/* register is not live, just remove spill/reload */
|
||||||
node->link->v.w = jit_regload_isdead;
|
node->link->v.w = jit_regload_isdead;
|
||||||
del_node(prev, node);
|
del_node(prev, node);
|
||||||
|
@ -2615,7 +2616,7 @@ _patch_registers(jit_state_t *_jit)
|
||||||
regno = jit_regno(node->u.w);
|
regno = jit_regno(node->u.w);
|
||||||
if (node->v.w) {
|
if (node->v.w) {
|
||||||
if (node->v.w == jit_regload_isdead)
|
if (node->v.w == jit_regload_isdead)
|
||||||
jit_regset_clrbit(_jitc->reglive, regno);
|
jit_regset_clrbit(&_jitc->reglive, regno);
|
||||||
del_node(prev, node);
|
del_node(prev, node);
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue