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Add consistency check on temporaries during a jump

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* lib/jit_aarch64-cpu.c, lib/jit_aarch64-fpu.c,
	lib/jit_arm-cpu.c, lib/jit_arm-vfp.c,
	lib/jit_hppa-cpu.c, lib/jit_hppa-fpu.c,
	lib/jit_ia64-cpu.c, lib/jit_ia64-fpu.c,
	lib/jit_mips-cpu.c, lib/jit_mips-fpu.c,
	lib/jit_ppc-cpu.c, lib/jit_ppc-fpu.c,
	lib/jit_s390x-cpu.c, lib/jit_s390x-fpu.c,
	lib/jit_s390x.c, lib/jit_sparc-cpu.c,
	lib/jit_x86-cpu.c, lib/jit_x86-sse.c,
	lib/jit_x86-x87.c: Review generation of all branch
	instructions and always adds the jit_class_nospill
	bitfield for temporary registers that cannot be	spilled
	because the reload would be after a conditional jump; the
	patch only adds an extra assertion. These conditions do
	not happen on documented lightning usage, but can happen
	if one uses the not exported jit_get_reg and jit_unget_reg
	calls and cause enough register starvation.
This commit is contained in:
pcpa 2014-08-16 20:31:55 -03:00
parent 93e3ff38e1
commit b58960638d
20 changed files with 221 additions and 192 deletions
Download patch file Download diff file Expand all files Collapse all files

14
lib/jit_hppa-cpu.c
View file

@ -2294,7 +2294,7 @@ _bcmpi(jit_state_t *_jit, jit_word_t c, jit_word_t ci,
CMPIB_N_(ci, i1, r0, ((i0 - w) >> 2) - 2);
}
else {
reg = jit_get_reg(jit_class_gpr);
reg = jit_get_reg(jit_class_gpr|jit_class_nospill);
movi(rn(reg), i1);
w = _jit->pc.w;
CMPB_N_(c, r0, rn(reg), ((i0 - w) >> 2) - 2);
@ -2310,7 +2310,7 @@ _bmxr(jit_state_t *_jit, jit_bool_t c,
{
jit_word_t w;
jit_int32_t reg;
reg = jit_get_reg(jit_class_gpr);
reg = jit_get_reg(jit_class_gpr|jit_class_nospill);
andr(rn(reg), r0, r1);
w = c ? bnei(i0, rn(reg), 0) : beqi(i0, rn(reg), 0);
jit_unget_reg(reg);
@ -2323,7 +2323,7 @@ _bmxi(jit_state_t *_jit, jit_bool_t c,
{
jit_word_t w;
jit_int32_t reg;
reg = jit_get_reg(jit_class_gpr);
reg = jit_get_reg(jit_class_gpr|jit_class_nospill);
movi(rn(reg), i1);
andr(rn(reg), r0, rn(reg));
w = c ? bnei(i0, rn(reg), 0) : beqi(i0, rn(reg), 0);
@ -2352,7 +2352,7 @@ _boaddi(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
NOP();
}
else {
reg = jit_get_reg(jit_class_gpr);
reg = jit_get_reg(jit_class_gpr|jit_class_nospill);
movi(rn(reg), i1);
w = boaddr(i0, r0, rn(reg));
jit_unget_reg(reg);
@ -2381,7 +2381,7 @@ _boaddi_u(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
NOP();
}
else {
reg = jit_get_reg(jit_class_gpr);
reg = jit_get_reg(jit_class_gpr|jit_class_nospill);
movi(rn(reg), i1);
w = boaddr_u(i0, r0, rn(reg));
jit_unget_reg(reg);
@ -2410,7 +2410,7 @@ _bxaddi(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
NOP();
}
else {
reg = jit_get_reg(jit_class_gpr);
reg = jit_get_reg(jit_class_gpr|jit_class_nospill);
movi(rn(reg), i1);
w = bxaddr(i0, r0, rn(reg));
jit_unget_reg(reg);
@ -2439,7 +2439,7 @@ _bxaddi_u(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_word_t i1)
NOP();
}
else {
reg = jit_get_reg(jit_class_gpr);
reg = jit_get_reg(jit_class_gpr|jit_class_nospill);
movi(rn(reg), i1);
w = bxaddr_u(i0, r0, rn(reg));
jit_unget_reg(reg);