diff --git a/lightning/i386/asm-64.h b/lightning/i386/asm-64.h
index deaf1a8e3..9b882f9e3 100644
--- a/lightning/i386/asm-64.h
+++ b/lightning/i386/asm-64.h
@@ -297,9 +297,15 @@
 
 #define TESTQrr(RS, RD)			(_REXQrr(RS, RD),		_O_Mrm		(0x85		,_b11,_r8(RS),_r8(RD)				))
 #define TESTQrm(RS, MD, MB, MI, MS)	(_REXQrm(RS, MB, MI),		_O_r_X		(0x85		     ,_r8(RS)		,MD,MB,MI,MS		))
-#define TESTQir(IM, RD)			(!_s8P(IM) && (RD) == _RAX ? \
-                                        (_REXQrr(0, RD),                _O_L            (0xa9                                                   ,IM     )) : \
-                                        (_REXQrr(0, RD),                _O_Mrm_L        (0xf7           ,_b11,_b000  ,_r8(RD)                   ,IM     )) )
+#define TESTQir(IM, RD)							\
+    /* Immediate fits in 32 bits? */					\
+    (_s32P((long)(IM))							\
+     /* Yes. Immediate does not fit in 8 bits and reg is %rax? */	\
+     ? (!_s8P(IM) && (RD) == _RAX					\
+	? (_REXQrr(0, RD), _O_L(0xa9, IM))				\
+	: (_REXQrr(0, RD), _O_Mrm_L(0xf7, _b11, _b000, _r8(RD), IM)))	\
+     /* No. Need immediate in a register */				\
+     : (MOVQir(IM, JIT_REXTMP), TESTQrr(JIT_REXTMP, RD)))
 #define TESTQim(IM, MD, MB, MI, MS)	(_REXQrm(0, MB, MI),		_O_r_X_L	(0xf7		     ,_b000		,MD,MB,MI,MS	,IM	))
 
 #define CMPXCHGQrr(RS, RD)		(_REXQrr(RS, RD),		_OO_Mrm		(0x0fb1		,_b11,_r8(RS),_r8(RD)				))
diff --git a/lightning/i386/asm.h b/lightning/i386/asm.h
index 29f3ab149..8412ce7a0 100644
--- a/lightning/i386/asm.h
+++ b/lightning/i386/asm.h
@@ -337,9 +337,15 @@ enum {
 #define _ALUQrr(OP, RS, RD)		(_REXQrr(RS, RD),		_O_Mrm		(((OP) << 3) + 1,_b11,_r8(RS),_r8(RD)				))
 #define _ALUQmr(OP, MD, MB, MI, MS, RD)	(_REXQmr(MB, MI, RD),		_O_r_X		(((OP) << 3) + 3     ,_r8(RD)		,MD,MB,MI,MS		))
 #define _ALUQrm(OP, RS, MD, MB, MI, MS)	(_REXQrm(RS, MB, MI),		_O_r_X		(((OP) << 3) + 1     ,_r8(RS)		,MD,MB,MI,MS		))
-#define _ALUQir(OP, IM, RD)		(!_s8P(IM) && (RD) == _RAX ? \
-					(_REXQrr(0, RD),		_O_L		(((OP) << 3) + 5					,IM	)) : \
-					(_REXQrr(0, RD),		_Os_Mrm_sL	(0x81		,_b11,OP     ,_r8(RD)			,IM	)) )
+#define _ALUQir(OP, IM, RD)						\
+    /* Immediate fits in 32 bits? */					\
+    (_s32P((long)(IM))							\
+     /* Yes. Immediate does not fit in 8 bits and reg is %rax? */	\
+     ? (!_s8P(IM) && (RD) == _RAX					\
+	? (_REXQrr(0, RD), _O_L(((OP) << 3) + 5, IM))			\
+	: (_REXQrr(0, RD), _Os_Mrm_sL(0x81, _b11, OP, _r8(RD), IM)))	\
+     /* No. Need immediate in a register */				\
+     : (MOVQir(IM, JIT_REXTMP), _ALUQrr(OP, JIT_REXTMP, RD)))
 #define _ALUQim(OP, IM, MD, MB, MI, MS)	(_REXQrm(0, MB, MI),		_Os_r_X_sL	(0x81		     ,OP		,MD,MB,MI,MS	,IM	))
 
 #define ADCBrr(RS, RD)			_ALUBrr(X86_ADC, RS, RD)
diff --git a/lightning/i386/core-64.h b/lightning/i386/core-64.h
index 48a8996e4..12148500f 100644
--- a/lightning/i386/core-64.h
+++ b/lightning/i386/core-64.h
@@ -98,7 +98,7 @@ struct jit_local_state {
 
 #define jit_bra_l(rs, is, op) (_s32P((long)(is)) \
                                ? _jit_bra_l(rs, is, op) \
-                               : (MOVQir(is, JIT_REXTMP), jit_bra_qr(JIT_REXTMP, rs, op)))
+                               : (MOVQir(is, JIT_REXTMP), jit_bra_qr(rs, JIT_REXTMP, op)))
 
 /* When CMP with 0 can be replaced with TEST */
 #define jit_bra_l0(rs, is, op, op0)					\
@@ -307,8 +307,8 @@ static int jit_arg_reg_order[] = { _EDI, _ESI, _EDX, _ECX, _R8D, _R9D };
 #define jit_blei_ul(label, rs, is)	jit_bra_l0((rs), (is), JBEm(label), JEm(label) )
 #define jit_bgti_ul(label, rs, is)	jit_bra_l0((rs), (is), JAm(label), JNEm(label) )
 #define jit_bgei_ul(label, rs, is)	jit_bra_l ((rs), (is), JAEm(label)		    )
-#define jit_bmsi_l(label, rs, is) jit_bmsi_i(label, rs, is)
-#define jit_bmci_l(label, rs, is) jit_bmci_i(label, rs, is)
+#define jit_bmsi_l(label, rs, is)	(jit_reduceQ(TEST, (is), (rs)), JNZm(label), _jit.x.pc)
+#define jit_bmci_l(label, rs, is)	(jit_reduceQ(TEST, (is), (rs)), JZm(label),  _jit.x.pc)
 
 #define jit_pushr_l(rs) jit_pushr_i(rs)
 #define jit_popr_l(rs)  jit_popr_i(rs)