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Recognize RISC-V compilation targets.

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* module/system/base/target.scm (cpu-endianness): Add case for "riscv" variants.

Signed-off-by: Shea Levy <shea@shealevy.com>
Signed-off-by: Mark H Weaver <mhw@netris.org>
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Shea Levy 2018-02-25 20:34:39 -05:00 • committed by Mark H Weaver
parent 72d80a1ea3
commit d6e669b8cb
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module/system/base/target.scm
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@ -80,6 +80,8 @@
(endianness big)) (endianness big))
((string=? "aarch64" cpu) ((string=? "aarch64" cpu)
(endianness little)) (endianness little))
((string-match "riscv[1-9][0-9]*" cpu)
(endianness little))
(else (else
(error "unknown CPU endianness" cpu))))) (error "unknown CPU endianness" cpu)))))