diff --git a/ChangeLog b/ChangeLog
index 81d391916..f3ab5a042 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,11 @@
+2014-19-02 Paulo Andrade <pcpa@gnu.org>
+
+	* lib/jit_x86.c: Rewrite incorrect inline assembly that could
+	truncate a variable in a callee save register. Now it simply
+	tells gcc that the register is clobbered, instead of using a
+	*32 bit* swap with a temporary variable. The problem only
+	happens when compiling with optimization.
+
 2014-19-02 Paulo Andrade <pcpa@gnu.org>
 
 	* include/lightning/jit_aarch64.h, include/lightning/jit_arm.h,
diff --git a/lib/jit_x86.c b/lib/jit_x86.c
index 69df289e7..027e6db4c 100644
--- a/lib/jit_x86.c
+++ b/lib/jit_x86.c
@@ -236,10 +236,11 @@ jit_get_cpu(void)
 #endif
 
     /* query %eax = 1 function */
-    __asm__ volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
+    __asm__ volatile ("cpuid; movl %%ebx, %1"
 		      : "=a" (eax), "=r" (ebx),
 		      "=c" (ecx.cpuid), "=d" (edx.cpuid)
-		      : "0" (1));
+		      : "0" (1)
+		      : "ebx");
 
     jit_cpu.fpu		= edx.bits.fpu;
     jit_cpu.cmpxchg8b	= edx.bits.cmpxchg8b;
@@ -261,10 +262,11 @@ jit_get_cpu(void)
 
 #if __WORDSIZE == 64
     /* query %eax = 0x80000001 function */
-    __asm__ volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
+    __asm__ volatile ("cpuid; movl %%ebx, %1"
 		      : "=a" (eax), "=r" (ebx),
 		      "=c" (ecx.cpuid), "=d" (edx.cpuid)
-		      : "0" (0x80000001));
+		      : "0" (0x80000001)
+		      : "ebx");
     jit_cpu.lahf	= ecx.cpuid & 1;
 #endif
 }