Pass all but the (not yet implemented) qmul and qdiv tests in sparc

* check/float.tst: Add sparc to list of known NaN and +-Inf
	to integer conversion.

	* check/lightning.c: Define __sparc__ to preprocessor in
	the sparc backend.

	* include/lightning/jit_private.h: Correct wrong definition
	of emit_stxi_d, that has lived for a long time, but would
	cause problems whenever needing to spill/reload a float
	register.

	* include/lightning/jit_sparc.h: Can only use %g2,%g3,%g4
	for scratch variables, as other "global" registers are
	reserved for the system, e.g. libc.
	  Reorder float register naming to make it easier to
	access odd float registers, so that generating code for
	pusharg and getarg is easier for the IR.

	* lib/jit_mips-cpu.c, lib/jit_ppc-cpu.c: Update to match
	new code in jit_sparc-cpu.c. It must call jit_get_reg
	with jit_class_nospill if using the register to move
	an unconditional branch address to it, as the reload
	will not happen (actually could happen in the delay
	slot...)

	* lib/jit_sparc-cpu.c: Correct wrong macro definition for
	ldxr_s.
	  Properly implement div* and implement rem. Div* needs
	to use the y register, and rem* needs to be synthesized.
	  Correct b?sub* macro definitions.

	* lib/jit_sparc-fpu.c: Correct reversed float to/from double
	conversion.
	  Correct wrong jit_get_reg call asking for a gpr and then
	using the fpr with that number.
	  Correct wrong branch displacement computation for
	conditional branches.

	* lib/jit_sparc.c: Correct getarg_d and pushargi_d implementation.
	  Add rem* entries to the switch converting IR to machine code.

	* lib/lightning.c: Correct a problem detected when adding
	the jit_class_nospill flag to jit_get_reg, that was caused
	when having a branch to an "epilog" node, what would cause
	the code to think all registers in unknown state were live,
	while in truth, all registers in unknown state in the
	"just after return" point are actually dead.

lib/jit_sparc.c

@@ -39,9 +39,9 @@ jit_register_t		_rvs[] = {
     { rc(gpr) | 0x02,			"%g2" },
     { rc(gpr) | 0x03,			"%g3" },
     { rc(gpr) | 0x04,			"%g4" },
-    { rc(gpr) | 0x05,			"%g5" },
-    { rc(gpr) | 0x06,			"%g6" },
-    { rc(gpr) | 0x07,			"%g7" },
+    { 0x05,				"%g5" },
+    { 0x06,				"%g6" },
+    { 0x07,				"%g7" },
     { rc(arg) | rc(gpr) | 0x08,		"%o0" },
     { rc(arg) | rc(gpr) | 0x09,		"%o1" },
     { rc(arg) | rc(gpr) | 0x0a,		"%o2" },
@@ -67,13 +67,21 @@ jit_register_t		_rvs[] = {
     { rc(sav) | 0x1e,			"%fp" },
     { 0x1f,				"%i7" },
     { rc(fpr) | 0x00,			"%f0" },
+    { 0x01,				"%f1" },
     { rc(fpr) | 0x02,			"%f2" },
+    { 0x03,				"%f3" },
     { rc(fpr) | 0x04,			"%f4" },
+    { 0x05,				"%f5" },
     { rc(fpr) | 0x06,			"%f6" },
+    { 0x06,				"%f7" },
     { rc(fpr) | 0x08,			"%f8" },
+    { 0x09,				"%f9" },
     { rc(fpr) | 0x0a,			"%f10" },
+    { 0x0b,				"%f11" },
     { rc(fpr) | 0x0c,			"%f12" },
+    { 0x0d,				"%f13" },
     { rc(fpr) | 0x0e,			"%f14" },
+    { 0x0f,				"%f15" },
     { _NOREG,				"<none>" },
 };
 
@@ -364,12 +372,10 @@ _jit_getarg_d(jit_state_t *_jit, jit_int32_t u, jit_node_t *v)
     else if (v->u.w < 6) {
 	jit_stxi(-8, JIT_FP, _I0 + v->u.w);
 	jit_ldxi_f(u, JIT_FP, -8);
-	jit_ldxi_f(u, JIT_FP, stack_framesize);
-    }
-    else {
-	jit_ldxi_f(u, JIT_FP, v->u.w);
-	jit_ldxi_f(u + 1, JIT_FP, v->u.w + 4);
+	jit_ldxi_f(u + 1, JIT_FP, stack_framesize);
     }
+    else
+	jit_ldxi_d(u, JIT_FP, v->u.w);
 }
 
 void
@@ -469,7 +475,7 @@ _jit_pushargi_d(jit_state_t *_jit, jit_float64_t u)
 	_jit->function->call.argi += 2;
     }
     else if (_jit->function->call.argi < 6) {
-	jit_stxi_d(-8, JIT_FP, regno);
+	jit_stxi_f(-8, JIT_FP, regno);
 	jit_ldxi(_O0 + _jit->function->call.argi, JIT_FP, -8);
 	++_jit->function->call.argi;
 	jit_stxi_f(stack_framesize, JIT_SP, regno + 1);
@@ -713,6 +719,10 @@ _emit_code(jit_state_t *_jit)
 		case_rrw(div,);
 		case_rrr(div, _u);
 		case_rrw(div, _u);
+		case_rrr(rem,);
+		case_rrw(rem,);
+		case_rrr(rem, _u);
+		case_rrw(rem, _u);
 
 		case_rrr(and,);
 		case_rrw(and,);