From ee0fab1dae64f2f601dca7c67046bf5dd70ed4db Mon Sep 17 00:00:00 2001 From: pcpa Date: Thu, 6 Dec 2012 07:47:42 -0200 Subject: [PATCH] Correct testcases in the mips backend. * lib/jit_mips-fpu.c: Correct wrong register order in stxr_{f,d} in the mips backend. --- ChangeLog | 5 +++++ lib/jit_mips-fpu.c | 8 ++++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/ChangeLog b/ChangeLog index 825d973c1..f5b3a7c03 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,8 @@ +2012-12-05 Paulo Andrade + + * lib/jit_mips-fpu.c: Correct wrong register order in stxr_{f,d} + in the mips backend. + 2012-12-05 Paulo Andrade * lib/jit_arm-vfp.c: Correct regression found in armv7l with diff --git a/lib/jit_mips-fpu.c b/lib/jit_mips-fpu.c index 702a703fe..c4f51c667 100644 --- a/lib/jit_mips-fpu.c +++ b/lib/jit_mips-fpu.c @@ -686,8 +686,8 @@ _stxr_f(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2) { jit_int32_t reg; reg = jit_get_reg(jit_class_gpr); - addr(rn(reg), r1, r2); - str_f(rn(reg), r0); + addr(rn(reg), r0, r1); + str_f(rn(reg), r2); jit_unget_reg(reg); } @@ -916,8 +916,8 @@ _stxr_d(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2) { jit_int32_t reg; reg = jit_get_reg(jit_class_gpr); - addr(rn(reg), r1, r2); - str_d(rn(reg), r0); + addr(rn(reg), r0, r1); + str_d(rn(reg), r2); jit_unget_reg(reg); }