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New instructions load-f64, load-u64

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* libguile/instructions.c (FOR_EACH_INSTRUCTION_WORD_TYPE): Add word
  types for immediate f64 and u64 values.
  (TYPE_WIDTH): Bump up by a bit, now that we have 32 word types.
  (NOP, parse_instruction): Use 64-bit meta type.

* libguile/vm-engine.c (load-f64, load-u64): New instructions.

* module/language/bytecode.scm (compute-instruction-arity): Add parser
  for new instruction word types.

* module/language/cps/compile-bytecode.scm (compile-function): Add
  special-cased assemblers for new instructions, and also for scm->u64
  and u64->scm which I missed before.

* module/language/cps/effects-analysis.scm (load-f64, load-u64): New
  instructions.

* module/language/cps/slot-allocation.scm (compute-needs-slot): load-f64
  and load-u64 don't need slots.
  (compute-var-representations): Update for new instructions.

* module/language/cps/specialize-primcalls.scm (specialize-primcalls):
  Specialize scm->f64 and scm->u64 to make-f64 and make-u64.

* module/language/cps/types.scm (load-f64, load-u64): Wire up to type
  inference, though currently type inference only runs before
  specialization.

* module/language/cps/utils.scm (compute-defining-expressions): For some
  reason I don't understand, it's possible to see two definitions that
  are equal but not equal? here.  Allow for now.
  (compute-constant-values): Punch through type conversions to get
  constant u64/f64 values.

* module/system/vm/assembler.scm (assembler): Support for new word
  types.  Export the new assemblers.
This commit is contained in:
Andy Wingo 2015-11-20 16:14:32 +01:00
parent bdfa1c1b42
commit f34688ad25
11 changed files with 119 additions and 23 deletions
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14
libguile/instructions.c
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@ -50,6 +50,10 @@ SCM_SYMBOL (sym_bang, "!");
M(I32) /* Immediate. */ \
M(A32) /* Immediate, high bits. */ \
M(B32) /* Immediate, low bits. */ \
M(AF32) /* Immediate double, high bits. */ \
M(BF32) /* Immediate double, low bits. */ \
M(AU32) /* Immediate uint64, high bits. */ \
M(BU32) /* Immediate uint64, low bits. */ \
M(N32) /* Non-immediate. */ \
M(R32) /* Scheme value (indirected). */ \
M(L32) /* Label. */ \
@ -61,7 +65,7 @@ SCM_SYMBOL (sym_bang, "!");
M(B1_X7_F24) \
M(B1_X31)
#define TYPE_WIDTH 5
#define TYPE_WIDTH 6
enum word_type
{
@ -82,14 +86,14 @@ static SCM word_type_symbols[] =
/* The VM_DEFINE_OP macro uses a CPP-based DSL to describe what kinds of
arguments each instruction takes. This piece of code is the only
bit that actually interprets that language. These macro definitions
encode the operand types into bits in a 32-bit integer.
encode the operand types into bits in a 64-bit integer.
(instruction-list) parses those encoded values into lists of symbols,
one for each 32-bit word that the operator takes. This list is used
one for each 64-bit word that the operator takes. This list is used
by Scheme to generate assemblers and disassemblers for the
instructions. */
#define NOP SCM_T_UINT32_MAX
#define NOP SCM_T_UINT64_MAX
#define OP1(type0) \
(OP (0, type0))
#define OP2(type0, type1) \
@ -113,7 +117,7 @@ static SCM word_type_symbols[] =
/* Scheme interface */
static SCM
parse_instruction (scm_t_uint8 opcode, const char *name, scm_t_uint32 meta)
parse_instruction (scm_t_uint8 opcode, const char *name, scm_t_uint64 meta)
{
SCM tail = SCM_EOL;
int len;