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Code Activity
611 commits 61 branches 169 tags 73 MiB
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87 commits

Author SHA1 Message Date
Icecream95
a6fee1add8
Use bx instead of mov for jumps on ARM 2020-04-09 21:30:13 +12:00
Icecream95
7f5f26269f
Stop setting the thumb bit except on jumps to veneers 
Thanks to the previous commit, the jump targets should all be correct.
 2020-04-09 20:37:12 +12:00
Icecream95
8045386a45
Return a function pointer from jit_address 
This will allow supporting ARM code on armv7 without having to change
any users of Lightening.
 2020-04-09 20:26:35 +12:00
Icecream95
ba24ce465f
Use an rsh of 0 for jumps on ARM 
This will allow supporting jumping to ARM (as opposed to Thumb) code.
 2020-04-09 20:24:47 +12:00
Icecream95
aacaa6e38c
Add separate functions for veneer patching 2020-04-06 19:52:29 +12:00
Icecream95
297ae99c3f
Add flag bits to the jit_reloc_kind enum 2020-04-06 16:04:57 +12:00
Andy Wingo
a96c0188f1 Ensure 32 bytes of stack are reserved on 64-bit Windows targets 
* lightening/x86.c (reset_abi_arg_iterator): Reserve 32 stack bytes on
  64-bit Windows systems, in accordance with ABI.  Thanks a million to
  Charles Stanhope for the patch and to Mike Gran for testing!
 2020-02-17 22:01:14 +01:00
Andy Wingo
2db2b12e85 Fix mips32r6 bug 
See also:

https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=925129
http://hades.mech.northwestern.edu/images/1/16/MIPS32_Architecture_Volume_II-A_Instruction_Set.pdf
https://lists.gnu.org/archive/html/lightning/2019-08/msg00010.html
https://lists.gnu.org/archive/html/guile-devel/2019-08/msg00030.html

* lightening/mips-cpu.c: Fix encoding of LR.  Thanks to Bruno Haible.
 2020-01-06 21:58:04 +01:00
Andy Wingo
1c36f036f6 push/pop of link register does not affect stack size on x86 
* lightening/x86-cpu.c (pop_link_register, push_link_register): Don't
  record stack size changes here.
 2019-06-20 10:53:12 +02:00
Andy Wingo
62183fb098 Add jmpi_with_link instruction 
The existing calli / callr interface is for ABI calls.  Sometimes though
you want to call some of your own code, just to get the current return
address.  ARM's branch-and-link instructions are ideal for this but they
don't exist on x86; there we emulate them by adding corresponding
pop_link_register / push_link_register instructions that are no-ops on
ARM.

* lightening.h (FOR_EACH_INSTRUCTION): Add jit_jmpi_with_link,
  pop_link_register, push_link_register.
* lightening/arm-cpu.c:
* lightening/x86-cpu.c:
* lightening/aarch64-cpu.c (jmpi_with_link, push_link_register)
  (pop_link_register): Add implementations.
* lightening/arm.h:
* lightening/aarch64.h:
* lightening/x86.h (JIT_LR): New definition.
* tests/link-register.c: New test.
 2019-06-20 10:13:37 +02:00
Andy Wingo
84b9ef087b Add breakpoint instruction 2019-05-27 18:29:26 +02:00
Andy Wingo
23bfbbaac1 Fix accidental change to ARMv7 ldr 2019-05-27 13:52:36 +02:00
Andy Wingo
bcdde6656b Add atomic operations 
These operations emit the same code that GCC does for corresponding
operations under the sequential consistency memory model.  It would be
possible to relax to acquire/release or something in the future.
 2019-05-27 11:34:13 +02:00
Andy Wingo
909c0077cc Correctly handle overflow when emitting literal pools 2019-05-27 11:34:13 +02:00
Andy Wingo
ff6ab1d2b1 Silence "unused" warnings 2019-05-22 23:04:30 +02:00
Andy Wingo
0b3393415e Allow add_pending_literal to return false 
This avoids invalidating offsets for the reloc.
 2019-05-22 17:29:10 +02:00
Andy Wingo
b67c4ed1e1 Avoid recursive pool emit for aarch64; add another overflow check 2019-05-21 16:05:03 +02:00
Andy Wingo
33754ba8c7 AArch64 fix 2019-05-21 15:34:40 +02:00
Andy Wingo
b7f367165f Various fixes for as-needed emission of literal pool 2019-05-21 15:25:08 +02:00
Andy Wingo
568fdecc86 Fix literal pool emission on armv7 2019-05-21 14:19:48 +02:00
Andy Wingo
0518651bfd Expose API to bless function pointers 
On ARMv7, we need to set the low bit to indicate that we're in
thumb-land.
 2019-05-21 14:00:04 +02:00
Andy Wingo
ef7abb568a Fix typo in previous commit, doh 2019-05-21 12:44:00 +02:00
Andy Wingo
d2c15dd6cd Clear literal pool more thoroughly 2019-05-21 12:38:53 +02:00
Andy Wingo
723f70ee11 Clear missing bit from literal pool 2019-05-21 12:24:20 +02:00
Andy Wingo
f49752eac0 Avoid using x18 on AArch64 2019-05-21 12:02:40 +02:00
Andy Wingo
58fc136722 Fix bounds checking on negative ldr offsets for aarch64 2019-05-20 21:35:42 +02:00
Andy Wingo
0b723c0401 ARMv7 backend passing all tests! 2019-05-20 15:20:33 +02:00
Andy Wingo
7dd18bddd7 ARMv7 backend compiling without warnings 2019-05-20 11:02:21 +02:00
Andy Wingo
8ce07131f1 Beginnings of VFP port to lightening 2019-05-19 23:29:10 +02:00
Andy Wingo
1ea34693cb Port of arm-cpu.c to current lightening 2019-05-19 22:21:50 +02:00
Andy Wingo
b71ddba1f7 Beginnings of ARMv7 backend 2019-05-17 10:59:59 +02:00
Andy Wingo
0da87968d1 Remove unused jit_{gpr,fpr}_is_callee_save 2019-05-17 10:59:05 +02:00
Andy Wingo
eaf702765d Remove software floating-point ARMv7 support; ARMv7 test env 2019-05-17 09:39:01 +02:00
Andy Wingo
9d4185af2b Remove jit_nop 
Instead, jit_align will call nop() internally.  You can't nop 3 bytes on
most architectures.
 2019-05-16 11:40:24 +02:00
Andy Wingo
f2d7321504 Aarch64 backend avoids needless temporary register allocation 2019-05-16 11:31:50 +02:00
Andy Wingo
9638e4f169 Fix a couple bugs related to aarch64 literal pools 2019-05-16 11:03:49 +02:00
Andy Wingo
9c9389ad2b Fix enter/leave JIT ABI 2019-05-16 10:45:44 +02:00
Andy Wingo
a643f99d68 Fix compilation on aarch64 2019-05-16 10:19:02 +02:00
Andy Wingo
7e0b0be1ba Fix GPR temporary selection 2019-05-15 16:26:18 +02:00
Andy Wingo
09e71475f4 Allow a backend to have multiple temporary registers 2019-05-15 16:19:33 +02:00
Andy Wingo
5b8262e804 Rework register saving to avoid push/pop 
Push and pop are not well supported on AArch64, so we might as well just
bump the stack pointer once and fill in by offset.
 2019-05-15 15:41:02 +02:00
Andy Wingo
0bfdcc7016 Refactor to add support for constant tables, shifted relocs 2019-05-14 15:53:25 +02:00
Andy Wingo
19e7712358 First pass at aarch64 assembler port 2019-05-14 15:46:19 +02:00
Andy Wingo
fc9b474da6 Refactor some bits from x86 to lightening 2019-05-10 14:14:32 +02:00
Andy Wingo
f7080facb4 Refactor to move temp register acquire to core 2019-05-09 16:02:39 +02:00
Andy Wingo
570f361c6c Remove Sparc support 
Sadly, this is a dead architecture, without an official Debian port.
Rest in peace!
 2019-05-08 21:44:03 +02:00
Andy Wingo
ced3c42dee Remove hppa support 
This is a dead architecture without an official Debian port.
 2019-05-08 21:44:03 +02:00
Andy Wingo
d51bd7d592 Remove alpha support 
This is a dead architecture without an official Debian port.
 2019-05-08 21:44:01 +02:00
Andy Wingo
80f79fca93 Remove ia64 (itanium) support 
This is a dead architecture without an official Debian port.
 2019-05-08 21:37:40 +02:00
Andy Wingo
d6eea0b499 Attempt to pop x87 stack 2019-04-29 17:15:46 +02:00