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Author SHA1 Message Date
pcpa
b663d29bea Correct race condition if register is written more than once
* lib/jit_ia64-cpu.c, lib/jit_ia64-fpu.c: Correct code to
	also insert a stop to break an instruction group if a
	register is written more than once in the same group.
	This may happen if a register is argument and result of
	some lightning call (not a real instruction). The most
	common case should be code in the pattern:
		movl rn=largenum
		...
		mov rn=smallnum
	where "rn" would end up holding "largenum".
	But the problem possibly could happen in other circumstances.
2013-04-26 21:26:00 -03:00
pcpa
746f3bb6c7 Correct jit implementation to pass several test cases.
* include/lightning/jit_ia64.h, lib/jit_ia64-cpu.c,
	lib/jit_ia64-fpu.c, lib/jit_ia64.c:
	  Relocate JIT_Rn registers to the local registers, as, like
	float registers, div/rem and sqrt are implemented as function
	calls, and may overwrite non saved scratch registers.
	  Change patch_at to receive a jit_code_t instead of a
	jit_node_t, so that it is easier to "inline" patches when
	some instruction requires complex code to implement, e.g.
	uneq and ltgt.
	  Correct arguments to FMA and FMA like instructions that,
	due to a cut&paste error were passing the wrong argument
	to the related F- implementation function.
	  Rewrite ltgt to return the proper result if one (or both)
	of the arguments is unordered.
2013-04-26 21:07:40 -03:00
pcpa
89f1e2f608 Properly split instruction groups for predicate registers.
* include/lightning/jit_ia64.h, include/lightning/jit_private.h,
	lib/jit_ia64-cpu.c, lib/jit_ia64-fpu.c, lib/jit_ia64.c,
	lib/lightning.c: Rework code to detect need of a "stop" to
	also handle predicates, as if a predicate is written, it
	cannot be read in the same instruction group.
	  Use a single jit_regset_t variable for all registers when
	checking need for a stop (increment value by 128 for
	float registers).
	  Correct wrong "subi" implementation, as the code executed
	is r0=im-r1, not r0=r1-im.
	  Use standard lightning 6 fpr registers, and rework to
	use callee save float registers, that may be spill/reloaded
	in prolog/epilog. This is required because some jit
	instructions implementations need to call functions; currently
	integer div/mod and float sqrt, what may change the value of
	scratch float registers.
	  Rework point of "sync" of branches that need to return a
	patch'able address, because the need for a "stop" before a
	predicate read causes all branches to be the instruction
	in slot 0, as there is no template to "stop" and branch
	in the same instruction "bundle".
2013-04-26 06:02:29 -03:00
pcpa
c2e4eb621d Add basic Itanium port infrastructure.
* include/lightning/jit_ia64.h, lib/jit_ia64-cpu.c,
	lib/jit_ia64-fpu.c, lib/jit_ia64.c: New files implementing
	the basic infrastructure of an Itanium port. The code
	compiles and can generate jit for basic hello world like
	functions.

	* check/lightning.c, configure.ac, include/lightning.h,
	include/lightning/Makefile.am, include/lightning/jit_private.h,
	lib/Makefile.am, lib/lightning.c: Update for the Itanium
	port.

	* lib/jit_mips-cpu.c, lib/jit_mips.c: Correct typo and
	make the jit_carry register local to the jit_state_t.
	This matches code reviewed in the Itanium port, that
	should use the same base logic to handle carry/borrow.
2013-04-25 21:56:32 -03:00