Shea Levy 2662cafd6a Recognize RISC-V compilation targets. ... * module/system/base/target.scm (cpu-endianness): Add case for "riscv" variants. Signed-off-by: Shea Levy <shea@shealevy.com> Signed-off-by: Mark H Weaver <mhw@netris.org>		2018-08-07 11:40:46 +02:00
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ice-9	Revert "Honor '%fresh-auto-compile'."	2018-08-07 11:37:11 +02:00
language	Compile current-module as intrinsic call	2018-06-27 14:57:51 +02:00
oop	Add new vtable reserved unboxed field	2017-09-26 20:47:27 +02:00
rnrs	Replace "pr" struct fields with "pw" fields	2017-09-23 15:33:02 +02:00
scripts	compile: Load language modules upfront.	2018-08-07 11:35:34 +02:00
srfi	srfi-18: 'thread-sleep!' timeout-as-a-number is relative.	2018-08-07 11:40:40 +02:00
sxml	Remove duplicate definitions of call/ec' and let/ec'.	2013-04-06 15:40:19 +02:00
system	Recognize RISC-V compilation targets.	2018-08-07 11:40:46 +02:00
texinfo	Remove all deprecated code	2017-05-22 13:36:42 +02:00
web	Merge until 2fe9a852fb from stable-2.2	2017-11-29 21:12:01 +01:00
Makefile.am	Add (system base optimize) module	2018-01-05 10:19:54 +01:00
rnrs.scm	Add R6RS bytevector->string, string->bytevector	2016-06-21 11:29:14 +02:00
statprof.scm	Remove all deprecated code	2017-05-22 13:36:42 +02:00
texinfo.scm	texinfo: fix @url{@@} parsing	2014-11-09 15:56:33 +00:00