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https://git.savannah.gnu.org/git/guile.git
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f31fb0044d
The problem with callr is that the register that contains the function to be called, can be overwritten by the logic that moves the values into argument registers. To fix this, I added a get_callr_temp function that should return a platform specific register that is not used to pass arguments. For Aarch64/Arm the link registers seems to work; for Amd64/i686 the RAX register. The function/tmp pair becomes an additional argument to the parallel assigment; this way the original function register is not accidentally overwritten. The problem with calli is that it may not have enough temp registers to move arguments. The windmill paper says that at most one temporary register is needed for the parallel assignment. However, we also need a temp register for mem-to-mem moves. So it seems that we need a second temporary. For Amd64/i686 we have only one temporary GPR and one temporary FPR. To fix this, I modified the algorithm from the paper a bit: we perform the mem-to-mem moves before the other moves. Later when we need the temp to break cycles, there shouldn't be any mem-to-mem moves left. So we should never need two temps at the same time. * lightening/lightening.c: (get_callr_temp): New function; need for each platform. (prepare_call_args): Include the function/callr_temp pair in the arguments for the parallel assignment. * lightening/x86.c, lightening/arm.c, lightening/aarch64.c (get_callr_temp): Implementation for each platform. * lightening/arm.c (next_abi_arg): Fix the stack size for doubles. * tests/call_10_2.c, tests/callr_10.c: New tests. * tests/regarrays.inc: New file. Common code between the above two tests that would be tedious to duplicate.
413 lines
11 KiB
C
413 lines
11 KiB
C
/*
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* Copyright (C) 2012-2020 Free Software Foundation, Inc.
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*
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* This file is part of GNU lightning.
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*
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* GNU lightning is free software; you can redistribute it and/or modify it
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* under the terms of the GNU Lesser General Public License as published
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* by the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* GNU lightning is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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* License for more details.
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*
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* Authors:
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* Paulo Cesar Pereira de Andrade
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*/
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#define _NOREG 0xffff
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typedef struct {
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/* x87 present */
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uint32_t fpu : 1;
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/* cmpxchg8b instruction */
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uint32_t cmpxchg8b : 1;
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/* cmov and fcmov branchless conditional mov */
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uint32_t cmov : 1;
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/* mmx registers/instructions available */
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uint32_t mmx : 1;
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/* sse registers/instructions available */
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uint32_t sse : 1;
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/* sse2 registers/instructions available */
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uint32_t sse2 : 1;
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/* sse3 instructions available */
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uint32_t sse3 : 1;
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/* pcmulqdq instruction */
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uint32_t pclmulqdq : 1;
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/* ssse3 suplemental sse3 instructions available */
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uint32_t ssse3 : 1;
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/* fused multiply/add using ymm state */
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uint32_t fma : 1;
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/* cmpxchg16b instruction */
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uint32_t cmpxchg16b : 1;
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/* sse4.1 instructions available */
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uint32_t sse4_1 : 1;
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/* sse4.2 instructions available */
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uint32_t sse4_2 : 1;
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/* movbe instruction available */
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uint32_t movbe : 1;
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/* popcnt instruction available */
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uint32_t popcnt : 1;
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/* aes instructions available */
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uint32_t aes : 1;
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/* avx instructions available */
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uint32_t avx : 1;
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/* lahf/sahf available in 64 bits mode */
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uint32_t lahf : 1;
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} jit_cpu_t;
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static jit_cpu_t jit_cpu;
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static inline jit_reloc_t
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emit_rel8_reloc (jit_state_t *_jit, uint8_t inst_start)
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{
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uint8_t *loc = _jit->pc.uc;
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emit_u8 (_jit, 0);
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return jit_reloc(_jit, JIT_RELOC_REL8, inst_start, loc, _jit->pc.uc, 0);
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}
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static inline jit_reloc_t
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emit_rel32_reloc (jit_state_t *_jit, uint8_t inst_start)
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{
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uint8_t *loc = _jit->pc.uc;
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emit_u32 (_jit, 0);
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return jit_reloc(_jit, JIT_RELOC_REL32, inst_start, loc, _jit->pc.uc, 0);
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}
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#include "x86-cpu.c"
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#include "x86-sse.c"
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jit_bool_t
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jit_get_cpu(void)
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{
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union {
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struct {
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uint32_t sse3 : 1;
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uint32_t pclmulqdq : 1;
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uint32_t dtes64 : 1; /* amd reserved */
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uint32_t monitor : 1;
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uint32_t ds_cpl : 1; /* amd reserved */
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uint32_t vmx : 1; /* amd reserved */
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uint32_t smx : 1; /* amd reserved */
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uint32_t est : 1; /* amd reserved */
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uint32_t tm2 : 1; /* amd reserved */
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uint32_t ssse3 : 1;
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uint32_t cntx_id : 1; /* amd reserved */
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uint32_t __reserved0 : 1;
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uint32_t fma : 1;
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uint32_t cmpxchg16b : 1;
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uint32_t xtpr : 1; /* amd reserved */
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uint32_t pdcm : 1; /* amd reserved */
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uint32_t __reserved1 : 1;
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uint32_t pcid : 1; /* amd reserved */
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uint32_t dca : 1; /* amd reserved */
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uint32_t sse4_1 : 1;
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uint32_t sse4_2 : 1;
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uint32_t x2apic : 1; /* amd reserved */
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uint32_t movbe : 1; /* amd reserved */
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uint32_t popcnt : 1;
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uint32_t tsc : 1; /* amd reserved */
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uint32_t aes : 1;
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uint32_t xsave : 1;
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uint32_t osxsave : 1;
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uint32_t avx : 1;
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uint32_t __reserved2 : 1; /* amd F16C */
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uint32_t __reserved3 : 1;
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uint32_t __alwayszero : 1; /* amd RAZ */
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} bits;
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jit_uword_t cpuid;
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} ecx;
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union {
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struct {
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uint32_t fpu : 1;
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uint32_t vme : 1;
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uint32_t de : 1;
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uint32_t pse : 1;
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uint32_t tsc : 1;
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uint32_t msr : 1;
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uint32_t pae : 1;
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uint32_t mce : 1;
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uint32_t cmpxchg8b : 1;
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uint32_t apic : 1;
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uint32_t __reserved0 : 1;
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uint32_t sep : 1;
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uint32_t mtrr : 1;
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uint32_t pge : 1;
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uint32_t mca : 1;
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uint32_t cmov : 1;
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uint32_t pat : 1;
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uint32_t pse36 : 1;
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uint32_t psn : 1; /* amd reserved */
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uint32_t clfsh : 1;
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uint32_t __reserved1 : 1;
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uint32_t ds : 1; /* amd reserved */
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uint32_t acpi : 1; /* amd reserved */
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uint32_t mmx : 1;
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uint32_t fxsr : 1;
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uint32_t sse : 1;
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uint32_t sse2 : 1;
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uint32_t ss : 1; /* amd reserved */
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uint32_t htt : 1;
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uint32_t tm : 1; /* amd reserved */
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uint32_t __reserved2 : 1;
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uint32_t pbe : 1; /* amd reserved */
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} bits;
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jit_uword_t cpuid;
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} edx;
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#if __X32
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int ac, flags;
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#endif
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jit_uword_t eax, ebx;
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#if __X32
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/* adapted from glibc __sysconf */
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__asm__ volatile ("pushfl;\n\t"
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"popl %0;\n\t"
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"movl $0x240000, %1;\n\t"
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"xorl %0, %1;\n\t"
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"pushl %1;\n\t"
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"popfl;\n\t"
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"pushfl;\n\t"
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"popl %1;\n\t"
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"xorl %0, %1;\n\t"
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"pushl %0;\n\t"
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"popfl"
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: "=r" (flags), "=r" (ac));
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/* i386 or i486 without cpuid */
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if ((ac & (1 << 21)) == 0)
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/* probably without x87 as well */
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return 0;
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#endif
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/* query %eax = 1 function */
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__asm__ volatile (
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#if __X32 || __X64_32
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"xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
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#else
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"xchgq %%rbx, %1; cpuid; xchgq %%rbx, %1"
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#endif
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: "=a" (eax), "=r" (ebx),
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"=c" (ecx.cpuid), "=d" (edx.cpuid)
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: "0" (1));
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jit_cpu.fpu = edx.bits.fpu;
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jit_cpu.cmpxchg8b = edx.bits.cmpxchg8b;
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jit_cpu.cmov = edx.bits.cmov;
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jit_cpu.mmx = edx.bits.mmx;
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jit_cpu.sse = edx.bits.sse;
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jit_cpu.sse2 = edx.bits.sse2;
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jit_cpu.sse3 = ecx.bits.sse3;
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jit_cpu.pclmulqdq = ecx.bits.pclmulqdq;
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jit_cpu.ssse3 = ecx.bits.ssse3;
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jit_cpu.fma = ecx.bits.fma;
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jit_cpu.cmpxchg16b = ecx.bits.cmpxchg16b;
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jit_cpu.sse4_1 = ecx.bits.sse4_1;
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jit_cpu.sse4_2 = ecx.bits.sse4_2;
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jit_cpu.movbe = ecx.bits.movbe;
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jit_cpu.popcnt = ecx.bits.popcnt;
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jit_cpu.aes = ecx.bits.aes;
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jit_cpu.avx = ecx.bits.avx;
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/* query %eax = 0x80000001 function */
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#if __X64
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__asm__ volatile (
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# if __X64_32
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"xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
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# else
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"xchgq %%rbx, %1; cpuid; xchgq %%rbx, %1"
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# endif
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: "=a" (eax), "=r" (ebx),
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"=c" (ecx.cpuid), "=d" (edx.cpuid)
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: "0" (0x80000001));
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jit_cpu.lahf = ecx.cpuid & 1;
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#endif
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return jit_cpu.sse2;
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}
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jit_bool_t
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jit_init(jit_state_t *_jit)
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{
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return jit_cpu.sse2;
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}
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static const jit_gpr_t abi_gpr_args[] = {
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#if __X32
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/* No GPRs in args. */
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#elif __CYGWIN__
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_RCX, _RDX, _R8, _R9
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#else
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_RDI, _RSI, _RDX, _RCX, _R8, _R9
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#endif
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};
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static const jit_fpr_t abi_fpr_args[] = {
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#if __X32
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/* No FPRs in args. */
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#elif __CYGWIN__
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_XMM0, _XMM1, _XMM2, _XMM3
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#else
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_XMM0, _XMM1, _XMM2, _XMM3, _XMM4, _XMM5, _XMM6, _XMM7
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#endif
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};
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static const int abi_gpr_arg_count = sizeof(abi_gpr_args) / sizeof(abi_gpr_args[0]);
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static const int abi_fpr_arg_count = sizeof(abi_fpr_args) / sizeof(abi_fpr_args[0]);
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struct abi_arg_iterator
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{
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const jit_operand_t *args;
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size_t argc;
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size_t arg_idx;
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size_t gpr_idx;
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size_t fpr_idx;
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size_t stack_size;
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size_t stack_padding;
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};
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static size_t
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jit_operand_abi_sizeof(enum jit_operand_abi abi)
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{
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switch (abi) {
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case JIT_OPERAND_ABI_UINT8:
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case JIT_OPERAND_ABI_INT8:
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return 1;
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case JIT_OPERAND_ABI_UINT16:
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case JIT_OPERAND_ABI_INT16:
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return 2;
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case JIT_OPERAND_ABI_UINT32:
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case JIT_OPERAND_ABI_INT32:
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return 4;
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case JIT_OPERAND_ABI_UINT64:
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case JIT_OPERAND_ABI_INT64:
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return 8;
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case JIT_OPERAND_ABI_POINTER:
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return CHOOSE_32_64(4, 8);
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case JIT_OPERAND_ABI_FLOAT:
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return 4;
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case JIT_OPERAND_ABI_DOUBLE:
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return 8;
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default:
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abort();
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}
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}
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static size_t
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round_size_up_to_words(size_t bytes)
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{
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size_t word_size = CHOOSE_32_64(4, 8);
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size_t words = (bytes + word_size - 1) / word_size;
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return words * word_size;
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}
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static size_t
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jit_initial_frame_size (void)
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{
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return __WORDSIZE / 8; // Saved return address is on stack.
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}
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static void
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reset_abi_arg_iterator(struct abi_arg_iterator *iter, size_t argc,
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const jit_operand_t *args)
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{
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memset(iter, 0, sizeof *iter);
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iter->argc = argc;
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iter->args = args;
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#if __CYGWIN__ && __X64
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// Reserve slots on the stack for 4 register parameters (8 bytes each).
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iter->stack_size = 32;
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#endif
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}
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static void
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next_abi_arg(struct abi_arg_iterator *iter, jit_operand_t *arg)
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{
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ASSERT(iter->arg_idx < iter->argc);
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enum jit_operand_abi abi = iter->args[iter->arg_idx].abi;
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if (is_gpr_arg(abi) && iter->gpr_idx < abi_gpr_arg_count) {
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*arg = jit_operand_gpr (abi, abi_gpr_args[iter->gpr_idx++]);
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#ifdef __CYGWIN__
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iter->fpr_idx++;
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#endif
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} else if (is_fpr_arg(abi) && iter->fpr_idx < abi_fpr_arg_count) {
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*arg = jit_operand_fpr (abi, abi_fpr_args[iter->fpr_idx++]);
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#ifdef __CYGWIN__
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iter->gpr_idx++;
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#endif
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} else {
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*arg = jit_operand_mem (abi, JIT_SP, iter->stack_size);
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size_t bytes = jit_operand_abi_sizeof (abi);
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iter->stack_size += round_size_up_to_words (bytes);
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}
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iter->arg_idx++;
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}
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static void
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jit_flush(void *fptr, void *tptr)
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{
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}
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static inline size_t
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jit_stack_alignment(void)
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{
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return 16;
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}
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static void
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jit_try_shorten(jit_state_t *_jit, jit_reloc_t reloc, jit_pointer_t addr)
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{
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uint8_t *loc = _jit->start + reloc.offset;
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uint8_t *start = loc - reloc.inst_start_offset;
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uint8_t *end = _jit->pc.uc;
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jit_imm_t i0 = (jit_imm_t)addr;
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if (loc == start)
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return;
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if (start < (uint8_t*)addr && (uint8_t*)addr <= end)
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return;
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switch (reloc.kind)
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{
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case JIT_RELOC_ABSOLUTE: {
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_jit->pc.uc = start;
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ASSERT((loc[-1] & ~7) == 0xb8); // MOVI
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int32_t r0 = loc[-1] & 7;
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if (start != loc - 1) {
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ASSERT(start == loc - 2);
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r0 |= (loc[-2] & 1) << 3;
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}
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return movi(_jit, r0, i0);
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}
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case JIT_RELOC_REL8:
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ASSERT((loc[-1] & ~0xf) == 0x70 || loc[-1] == 0xeb); // JCCSI or JMPSI
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/* Nothing useful to do. */
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return;
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case JIT_RELOC_REL32:
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_jit->pc.uc = start;
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if (start[0] == 0xe9) { // JMP
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return jmpi(_jit, i0);
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}
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ASSERT(start[0] == 0x0f); // JCC
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return jcci(_jit, start[1] & ~0x80, i0);
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default:
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/* We don't emit other kinds of reloc. */
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abort ();
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}
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}
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static void*
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bless_function_pointer(void *ptr)
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{
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return ptr;
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}
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static jit_gpr_t
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get_callr_temp (jit_state_t * _jit)
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{
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return _RAX;
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}
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