Shea Levy 2662cafd6a Recognize RISC-V compilation targets. ... * module/system/base/target.scm (cpu-endianness): Add case for "riscv" variants. Signed-off-by: Shea Levy <shea@shealevy.com> Signed-off-by: Mark H Weaver <mhw@netris.org>		2018-08-07 11:40:46 +02:00
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base	Recognize RISC-V compilation targets.	2018-08-07 11:40:46 +02:00
repl	Update --version and REPL copyright years	2017-03-15 09:12:55 +01:00
vm	Compile current-module as intrinsic call	2018-06-27 14:57:51 +02:00
foreign-object.scm	Add #:static-slot-allocation?	2015-02-06 13:25:17 +01:00
foreign.scm	foreign: Add 'uintptr_t' and 'intptr_t'.	2017-11-22 16:33:57 +01:00
syntax.scm	Add disjoint syntax object type	2017-03-28 19:23:13 +02:00
xref.scm	Remove backend support for cached-module-box et al.	2018-05-14 14:04:59 +02:00