mirror of
https://https.git.savannah.gnu.org/git/guix.git/
synced 2025-07-10 16:50:43 +02:00
* gnu/packages/fpga.scm (gtkwave): Update to 3.4.0-0.bb978d9. [source]: Switch to git-fetch, new uri. [version]: Switch to branch master, version 3.4. [build-system]: Switch to meson-build-system. [arguments]: New field. [native-inputs]: Add desktop-file-utils, flex, glib:bin, gobject-introspection and gtk:bin. [inputs]: Add gtk and libfst. Remove gtk+:bin. [description]: Prefer @acronym to @dfn. [homepage]: Update URL. Change-Id: I38aabca14c2789ad7b3bc304b7018644dc6d0fa6 Signed-off-by: Maxim Cournoyer <maxim.cournoyer@gmail.com> Modified-by: Maxim Cournoyer <maxim.cournoyer@gmail.com>
833 lines
32 KiB
Scheme
833 lines
32 KiB
Scheme
;;; GNU Guix --- Functional package management for GNU
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;;; Copyright © 2016 Danny Milosavljevic <dannym@scratchpost.org>
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;;; Copyright © 2016, 2017 Theodoros Foradis <theodoros@foradis.org>
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;;; Copyright © 2018–2021 Tobias Geerinckx-Rice <me@tobias.gr>
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;;; Copyright © 2019 Amin Bandali <bandali@gnu.org>
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;;; Copyright © 2020 Vinicius Monego <monego@posteo.net>
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;;; Copyright © 2021 Andrew Miloradovsky <andrew@interpretmath.pw>
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;;; Copyright © 2022 Christian Gelinek <cgelinek@radlogic.com.au>
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;;; Copyright © 2022 jgart <jgart@dismail.de>
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;;; Copyright © 2023 Simon South <simon@simonsouth.net>
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;;; Copyright © 2024 Efraim Flashner <efraim@flashner.co.il>
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;;; Copyright © 2024 Jakob Kirsch <jakob.kirsch@web.de>
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;;; Copyright © 2025 Zheng Junjie <873216071@qq.com>
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;;; Copyright © 2025 Cayetano Santos <csantosb@inventati.org>
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;;; Copyright © 2025 Maxim Cournoyer <maxim.cournoyer@gmail.com>
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;;;
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;;; This file is part of GNU Guix.
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;;;
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;;; GNU Guix is free software; you can redistribute it and/or modify it
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;;; under the terms of the GNU General Public License as published by
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;;; the Free Software Foundation; either version 3 of the License, or (at
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;;; your option) any later version.
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;;;
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;;; GNU Guix is distributed in the hope that it will be useful, but
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;;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;;; GNU General Public License for more details.
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;;;
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;;; You should have received a copy of the GNU General Public License
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;;; along with GNU Guix. If not, see <http://www.gnu.org/licenses/>.
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(define-module (gnu packages fpga)
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#:use-module ((guix licenses) #:prefix license:)
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#:use-module (guix gexp)
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#:use-module (guix packages)
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#:use-module (guix deprecation)
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#:use-module (guix download)
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#:use-module (guix git-download)
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#:use-module (guix utils)
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#:use-module (guix build-system glib-or-gtk)
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#:use-module (guix build-system gnu)
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#:use-module (guix build-system cmake)
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#:use-module (guix build-system meson)
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#:use-module (guix build-system python)
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#:use-module (guix build-system pyproject)
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#:use-module (guix build-system qt)
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#:use-module (gnu packages)
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#:use-module (gnu packages autotools)
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#:use-module (gnu packages algebra)
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#:use-module (gnu packages base)
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#:use-module (gnu packages bash)
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#:use-module (gnu packages bison)
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#:use-module (gnu packages boost)
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#:use-module (gnu packages check)
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#:use-module (gnu packages cmake)
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#:use-module (gnu packages compression)
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#:use-module (gnu packages cpp)
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#:use-module (gnu packages elf)
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#:use-module (gnu packages flex)
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#:use-module (gnu packages freedesktop)
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#:use-module (gnu packages gawk)
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#:use-module (gnu packages gdb)
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#:use-module (gnu packages gettext)
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#:use-module (gnu packages ghostscript)
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#:use-module (gnu packages glib)
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#:use-module (gnu packages gperf)
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#:use-module (gnu packages graphviz)
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#:use-module (gnu packages gtk)
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#:use-module (gnu packages libffi)
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#:use-module (gnu packages libftdi)
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#:use-module (gnu packages libusb)
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#:use-module (gnu packages linux)
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#:use-module (gnu packages llvm)
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#:use-module (gnu packages man)
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#:use-module (gnu packages maths)
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#:use-module (gnu packages perl)
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#:use-module (gnu packages pkg-config)
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#:use-module (gnu packages python)
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#:use-module (gnu packages python-build)
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#:use-module (gnu packages python-check)
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#:use-module (gnu packages python-xyz)
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#:use-module (gnu packages ruby)
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#:use-module (gnu packages qt)
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#:use-module (gnu packages readline)
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#:use-module (gnu packages sphinx)
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#:use-module (gnu packages tcl)
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#:use-module (gnu packages texinfo)
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#:use-module (gnu packages toolkits)
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#:use-module (gnu packages version-control))
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(define-public abc
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(let ((commit "d2714035145bd237097c509c23fc9e24b0fa933b")
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(revision "5"))
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(package
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(name "abc")
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(version (git-version "0.0" revision commit))
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(source (origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/berkeley-abc/abc")
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(commit commit)))
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(file-name (git-file-name name version))
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(sha256
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(base32
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"10qjw6mbzwg2lgsscw759xrghqq2mvv0xcalpymngnjhpg9qznqk"))))
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(build-system gnu-build-system)
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(inputs
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(list readline))
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(arguments
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(list #:license-file-regexp "copyright.txt"
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#:tests? #f ; no tests
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#:phases
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#~(modify-phases %standard-phases
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(delete 'configure)
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(replace 'install
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(lambda _
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(install-file "abc" (string-append #$output "/bin")))))))
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(home-page "https://people.eecs.berkeley.edu/~alanmi/abc/")
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(synopsis "Sequential logic synthesis and formal verification")
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(description "ABC is a program for sequential logic synthesis and
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formal verification.")
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(license
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(license:non-copyleft
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"https://people.eecs.berkeley.edu/~alanmi/abc/copyright.htm")))))
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(define-public abc-yosyshq
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(package
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(inherit abc)
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(name "abc-yosyshq")
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(version "0.53")
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(source (origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/YosysHQ/abc/")
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(commit (string-append "v" version))))
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(file-name (git-file-name name version))
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(sha256
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(base32
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"15a7nyk8iqpadp326icnr7rn5pwq44b9lvajqc35hcsvixz4gxsa"))))
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(home-page "https://github.com/YosysHQ/abc/")
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(description "ABC is a program for sequential logic synthesis and
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formal verification. This is the Yosyshq fork of ABC.")
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(license (license:non-copyleft "file:///copyright.txt"))))
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(define-public iverilog
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(package
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(name "iverilog")
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(version "12.0")
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(source
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(origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/steveicarus/iverilog")
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(commit
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(string-append "v" (string-replace-substring version "." "_")))))
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(file-name (git-file-name name version))
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(sha256
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(base32 "1cm3ksxyyp8ihs0as5c2nk3a0y2db8dmrrw0f9an3sl255smxn17"))))
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(build-system gnu-build-system)
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(arguments
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(list
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#:make-flags #~(list (string-append "PREFIX=" #$output))
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#:bootstrap-scripts #~(list "autoconf.sh")))
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(native-inputs (list autoconf bison flex gperf))
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(inputs (list zlib))
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(home-page "https://steveicarus.github.io/iverilog/")
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(synopsis "FPGA Verilog simulation and synthesis tool")
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(description
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"Icarus Verilog is a Verilog simulation and synthesis tool.
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It operates as a compiler, compiling source code written in Verilog
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(IEEE-1364) into some target format.
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For batch simulation, the compiler can generate an intermediate form
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called vvp assembly.
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This intermediate form is executed by @command{vvp}.
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For synthesis, the compiler generates netlists in the desired format.")
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;; GPL2 only because of:
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;; - ./driver/iverilog.man.in
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;; - ./iverilog-vpi.man.in
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;; - ./tgt-fpga/iverilog-fpga.man
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;; - ./vvp/vvp.man.in
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;; Otherwise would be GPL2+.
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;; You have to accept both GPL2 and LGPL2.1+.
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(license (list license:gpl2 license:lgpl2.1+))))
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(define-public yosys
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(package
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(name "yosys")
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(version "0.53")
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(source
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(origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/YosysHQ/yosys")
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(commit (string-append "v" version))))
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(sha256
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(base32 "01pcf20dpm0gjfzr9bvw4w7cgc390gqg3xfnir9d6x0nr8k6lljh"))
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(file-name (git-file-name name version))))
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(build-system gnu-build-system)
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(arguments
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(list
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#:test-target "test"
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#:make-flags
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#~(list (string-append "CC="
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#$(cc-for-target))
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(string-append "CXX="
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#$(cxx-for-target))
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(string-append "PREFIX="
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#$output))
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#:phases
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#~(modify-phases %standard-phases
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(add-before 'configure 'fix-paths
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(lambda* (#:key inputs #:allow-other-keys)
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(substitute* "backends/smt2/smtio.py"
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(("\\['z3")
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(string-append "['"
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(search-input-file inputs "bin/z3"))))
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(substitute* "kernel/fstdata.cc"
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(("vcd2fst")
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(search-input-file inputs "bin/vcd2fst")))
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(substitute* "kernel/driver.cc"
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(("^#include \"libs/cxxopts/include/cxxopts.hpp\"")
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"#include <cxxopts.hpp>"))
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(substitute* '("passes/cmds/show.cc" "passes/cmds/viz.cc")
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(("exec xdot")
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(string-append "exec "
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(search-input-file inputs "bin/xdot")))
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(("dot -")
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(string-append (search-input-file inputs "bin/dot") " -"))
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(("fuser")
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(search-input-file inputs "bin/fuser")))))
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(replace 'configure
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(lambda* (#:key make-flags #:allow-other-keys)
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(apply invoke "make" "config-gcc" make-flags)))
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(add-after 'configure 'use-external-abc
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(lambda* (#:key inputs #:allow-other-keys)
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(substitute* '("Makefile")
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(("ABCEXTERNAL \\?=")
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(string-append "ABCEXTERNAL = "
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(search-input-file inputs "/bin/abc"))))))
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(add-after 'install 'add-symbolic-link
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(lambda* (#:key inputs #:allow-other-keys)
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;; Previously this package provided a copy of the "abc"
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;; executable in its output, named "yosys-abc". Create a
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;; symbolic link so any external uses of that name continue to
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;; work.
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(symlink (search-input-file inputs "/bin/abc")
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(string-append #$output "/bin/yosys-abc"))))
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(add-after 'install 'wrap
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(lambda* (#:key inputs #:allow-other-keys)
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(wrap-program (string-append #$output "/bin/yosys-witness")
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`("GUIX_PYTHONPATH" ":" prefix
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(,(getenv "GUIX_PYTHONPATH")))))))))
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(native-inputs (list bison
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cxxopts ;header-only library
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flex
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gawk ;for the tests and "make" progress pretty-printing
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iverilog ;for the tests
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pkg-config
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python
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tcl)) ;tclsh for the tests
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(inputs (list abc-yosyshq
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bash-minimal
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graphviz
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gtkwave
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libffi
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psmisc
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python
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python-click
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readline
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tcl
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xdot
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z3
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zlib))
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(home-page "https://yosyshq.net/yosys/")
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(synopsis "FPGA Verilog RTL synthesizer")
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(description "Yosys synthesizes Verilog-2005.")
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(license license:isc)))
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(define-public yosys-clang
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(package
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(inherit yosys)
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(name "yosys-clang")
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(arguments
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(substitute-keyword-arguments (package-arguments yosys)
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((#:make-flags _ #f)
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#~(list "CC=clang"
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"CXX=clang++"
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(string-append "PREFIX=" #$output)))
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((#:phases phases)
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#~(modify-phases #$phases
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(replace 'configure
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(lambda* (#:key make-flags #:allow-other-keys)
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(apply invoke "make" "config-clang" make-flags)))))))
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(inputs
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(modify-inputs (package-inputs yosys)
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(append clang)))
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(synopsis "FPGA Verilog RTL synthesizer (Clang variant)")))
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(define-public icestorm
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(let ((commit "3cdcf4b009bb8681ab7e2e09d65043f04334b60e")
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(revision "5"))
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(package
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(name "icestorm")
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(version (git-version "0.0" revision commit))
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(source
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(origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/YosysHQ/icestorm/")
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(commit commit)))
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(file-name (git-file-name name version))
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(sha256
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(base32 "0ygp6cj7grlnyji572kx215p2mw4crllskif9g795f390bp38g68"))))
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(build-system gnu-build-system)
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(arguments
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(list
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#:tests? #f ;avoid a cyclic dependency with nextpr-ice40
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#:make-flags
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#~(list (string-append "CC="
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#$(cc-for-target))
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(string-append "CXX="
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#$(cxx-for-target))
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(string-append "PREFIX="
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#$output)
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"ICEPROG=1")
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#:phases
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#~(modify-phases %standard-phases
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(add-after 'unpack 'fix-usr-local
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(lambda* (#:key outputs #:allow-other-keys)
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(substitute* "icepack/Makefile"
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(("/usr/local")
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#$output))
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(substitute* "icebox/Makefile"
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(("/usr/local")
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#$output))
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(substitute* "icebox/icebox_vlog.py"
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(("/usr/local")
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#$output))))
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(add-after 'build 'make-info
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(lambda* (#:key outputs #:allow-other-keys)
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(with-directory-excursion "docs"
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(invoke "make" "info")
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(install-file "build/texinfo/projecticestorm.info"
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(string-append #$output "/share/info"))
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(copy-recursively "build/texinfo/projecticestorm-figures"
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(string-append #$output
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"/share/info/projecticestorm-figures")))))
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(delete 'configure))))
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(inputs (list libftdi))
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(native-inputs (list pkg-config
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python
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python-sphinx
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python-sphinx-rtd-theme
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texinfo))
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(home-page "https://prjicestorm.readthedocs.io/")
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(synopsis "Bitstream tools for Lattice iCE40 FPGAs")
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(description
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"Project IceStorm aims at documenting the bitstream format of
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Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream
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files.")
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(license license:isc))))
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(define-public libfst
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;; There are no release nor tags.
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(let ((commit "6a52070cd62ec65c29832bc95e7db493504aa7ac")
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(revision "0"))
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(package
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(name "libfst")
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(version (git-version "1.0.0" revision commit))
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(source
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(origin
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(method git-fetch)
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(uri (git-reference
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(url "https://github.com/gtkwave/libfst/")
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(commit commit)))
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(file-name (git-file-name name version))
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(sha256
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(base32 "0b1r660m5aib316jjl4nhs10y7vhhqy2mvxjip3ynahig3hpi46z"))))
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(build-system meson-build-system)
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||
(native-inputs (list gobject-introspection pkg-config))
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(inputs (list bzip2))
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(propagated-inputs (list zlib)) ;in Requires.private of libfst.pc
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||
(synopsis "Fast Signal Trace (FST) format waveforms library")
|
||
(description "Libfst is a small library used to read and write
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@acronym{FST, Fast Signal Trace} format waveforms.")
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(home-page "https://github.com/gtkwave/libfst/")
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(license (list license:expat ;libfst and fastlz-derived sources
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license:bsd-2))))) ;for lz4-derived sources
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(define-public nextpnr
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(package
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(name "nextpnr")
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(version "0.8")
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(source
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(origin
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(method git-fetch)
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||
(uri (git-reference
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(url "https://github.com/YosysHQ/nextpnr/")
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(commit (string-append "nextpnr-" version))
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;; XXX: Fetch some bundled libraries such as QtPropertyBrowser,
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||
;; json11 and python-console, which have custom modifications or
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;; no longer have their original upstream.
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(recursive? #t)))
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(file-name (git-file-name name version))
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||
(modules '((guix build utils)
|
||
(ice-9 ftw)
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||
(srfi srfi-26)))
|
||
(snippet
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||
'(begin
|
||
;; XXX: 'delete-all-but' is copied from the turbovnc package.
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||
(define (delete-all-but directory . preserve)
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(define (directory? x)
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(and=> (stat x #f)
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(compose (cut eq? 'directory <>) stat:type)))
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||
(with-directory-excursion directory
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(let* ((pred
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(negate (cut member <> (append '("." "..") preserve))))
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(items (scandir "." pred)))
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(for-each (lambda (item)
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(if (directory? item)
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(delete-file-recursively item)
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(delete-file item)))
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items))))
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(delete-all-but "3rdparty"
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||
;; The following sources have all been patched, so
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||
;; cannot easily be unbundled.
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||
"QtPropertyBrowser"
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"json11"
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"python-console"
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"oourafft")))
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(patches (search-patches "nextpnr-gtest.patch"
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"nextpnr-imgui.patch"))
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||
(sha256
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(base32 "0p53a2gl89hf3hfwdxs6pykxyrk82j4lqpwd1fqia2y0c9r2gjlm"))))
|
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(build-system qt-build-system)
|
||
(arguments
|
||
(list
|
||
#:cmake cmake ;CMake 3.25 or higher is required.
|
||
#:configure-flags
|
||
#~(list "-DARCH=generic;ice40" ;TODO: enable more architectures?
|
||
"-DBUILD_GUI=ON"
|
||
"-DUSE_OPENMP=ON"
|
||
"-DBUILD_TESTS=ON"
|
||
(string-append "-DCURRENT_GIT_VERSION=nextpnr-" #$version)
|
||
(string-append "-DICESTORM_INSTALL_PREFIX="
|
||
#$(this-package-input "icestorm"))
|
||
"-DUSE_IPO=OFF")
|
||
#:phases
|
||
#~(modify-phases %standard-phases
|
||
(add-after 'unpack 'unbundle-sanitizers-cmake
|
||
(lambda* (#:key inputs #:allow-other-keys)
|
||
(substitute* "CMakeLists.txt"
|
||
;; Use the system sanitizers-cmake module. This is made
|
||
;; necessary 'sanitizers-cmake' installing a FindPackage
|
||
;; module but no CMake config file.
|
||
(("\\$\\{CMAKE_SOURCE_DIR}/3rdparty/sanitizers-cmake/cmake")
|
||
(string-append
|
||
#$(this-package-native-input "sanitizers-cmake")
|
||
"/share/sanitizers-cmake/cmake"))))))))
|
||
(native-inputs
|
||
(list googletest
|
||
sanitizers-cmake))
|
||
(inputs
|
||
(list boost
|
||
corrosion
|
||
eigen
|
||
icestorm
|
||
pybind11
|
||
python
|
||
qtbase-5
|
||
qtwayland-5
|
||
qtimgui
|
||
yosys))
|
||
(synopsis "Place-and-Route tool for FPGAs")
|
||
(description "Nextpnr is a portable FPGA place and route tool.")
|
||
(home-page "https://github.com/YosysHQ/nextpnr/")
|
||
(license license:isc)))
|
||
|
||
(define-public nextpnr-ice40
|
||
(deprecated-package "nextpnr-ice40" nextpnr))
|
||
|
||
(define-public gtkwave
|
||
;; The last release is more than 2 years old, and there are improvements in
|
||
;; the master branch, such as GTK 4 support: pick the latest commit that
|
||
;; passes their CI.
|
||
(let ((commit "bb978d9d667d569b9153ffa34007e300302907dc")
|
||
(revision "0"))
|
||
(package
|
||
(name "gtkwave")
|
||
;; The version string can be found in meson.build.
|
||
(version (git-version "3.4.0" revision commit))
|
||
(source
|
||
(origin
|
||
(method git-fetch)
|
||
(uri (git-reference
|
||
(url "https://github.com/gtkwave/gtkwave")
|
||
(commit commit)))
|
||
(file-name (git-file-name name version))
|
||
(sha256
|
||
(base32 "1nv27cpz5937cb6bkhpw8w0ji6hm9xr8f0znvfwzfl1fwwypf23y"))))
|
||
(build-system meson-build-system)
|
||
(arguments (list #:glib-or-gtk? #t))
|
||
(native-inputs (list desktop-file-utils
|
||
flex
|
||
`(,glib "bin") ;for glib-mkenums
|
||
gobject-introspection
|
||
gperf
|
||
`(,gtk "bin")
|
||
pkg-config))
|
||
(inputs (list gtk gtk+ libfst))
|
||
(synopsis "Waveform viewer for FPGA simulator trace files")
|
||
(description "This package is a waveform viewer for @acronym{FST, FPGA
|
||
Simulator Trace} files.")
|
||
(home-page "https://github.com/gtkwave/gtkwave")
|
||
;; Exception against free government use in tcl_np.c and tcl_np.h.
|
||
(license (list license:gpl2+ license:expat license:tcl/tk)))))
|
||
|
||
(define-public python-migen
|
||
;; XXX: The latest version tag (0.9.2) was placed in 2019, there are latest
|
||
;; changes supporting Python 3.11 on master branch, see
|
||
;; <https://github.com/m-labs/migen/issues/259>.
|
||
(let ((commit "2828df54594673653a641ab551caf6c6b1bfeee5")
|
||
(revision "0"))
|
||
(package
|
||
(name "python-migen")
|
||
(version (git-version "0.9.2" revision commit))
|
||
(source
|
||
(origin
|
||
;; Tests fail in the PyPI tarball due to missing files.
|
||
(method git-fetch)
|
||
(uri (git-reference
|
||
(url "https://github.com/m-labs/migen")
|
||
(commit commit)))
|
||
(file-name (git-file-name name version))
|
||
(sha256
|
||
(base32 "0my2jwrb64n39dfcipiw9s2cbg1r4s6zh4ybf4dwid9hk86fi6hs"))))
|
||
(build-system pyproject-build-system)
|
||
(native-inputs
|
||
(list python-pytest
|
||
python-setuptools
|
||
python-wheel))
|
||
(propagated-inputs
|
||
(list python-colorama))
|
||
(home-page "https://m-labs.hk/gateware/migen/")
|
||
(synopsis "Python toolbox for building complex digital hardware")
|
||
(description
|
||
"Migen FHDL is a Python library that replaces the event-driven paradigm
|
||
of Verilog and VHDL with the notions of combinatorial and synchronous
|
||
statements, has arithmetic rules that make integers always behave like
|
||
mathematical integers, and allows the design's logic to be constructed by a
|
||
Python program.")
|
||
(license license:bsd-2))))
|
||
|
||
(define-public python-myhdl
|
||
(package
|
||
(name "python-myhdl")
|
||
(version "0.11")
|
||
(source
|
||
(origin
|
||
(method url-fetch)
|
||
(uri (pypi-uri "myhdl" version))
|
||
(sha256
|
||
(base32
|
||
"04fi59cyn5dsci0ai7djg74ybkqfcjzhj1jfmac2xanbcrw9j3yk"))))
|
||
(build-system python-build-system)
|
||
(home-page "https://www.myhdl.org/")
|
||
(synopsis "Python as a Hardware Description Language")
|
||
(description "This package provides a library to turn Python into
|
||
a hardware description and verification language.")
|
||
(license license:lgpl2.1+)))
|
||
|
||
(define-public python-vunit
|
||
(package
|
||
(name "python-vunit")
|
||
(version "5.0.0-dev.5") ;v4.7.0 dates back from 2 years ago.
|
||
(source
|
||
(origin
|
||
(method git-fetch)
|
||
(uri (git-reference
|
||
(url "https://github.com/VUnit/vunit")
|
||
(commit (string-append "v" version))
|
||
(recursive? #t)))
|
||
(file-name (git-file-name name version))
|
||
(sha256
|
||
(base32 "1sfnl1l6bgaqa8c2sk8k8f232bnq2drjg6rg7jvscmyz18yfih0b"))))
|
||
(build-system pyproject-build-system)
|
||
(arguments
|
||
(list
|
||
#:test-flags
|
||
;; Skip lint tests which require python-pycodestyle, python-pylint and
|
||
;; python-mypy to reduce closoure size; some lint test fails, see
|
||
;; <https://github.com/VUnit/vunit/issues/1111>.
|
||
;;
|
||
;; XXX: Acceptance tests take 10+ minutes to complete, hang on
|
||
;; "test_external_run_scripts.py" and fail eventually, consider to
|
||
;; improve them; ignore for now.
|
||
#~(list "tests/unit")))
|
||
(native-inputs
|
||
(list nvc
|
||
python-pytest
|
||
python-setuptools
|
||
python-setuptools-scm
|
||
python-wheel))
|
||
(propagated-inputs
|
||
(list python-colorama))
|
||
(home-page "https://vunit.github.io")
|
||
(synopsis "Unit testing framework for VHDL/SystemVerilog")
|
||
(description
|
||
"VUnit features the functionality needed to realize continuous and
|
||
automated testing of HDL code.")
|
||
;; According to 'LICENSE.rst', VUnit itself is under MPL but two
|
||
;; subdirectories are under ASL.
|
||
(license (list license:mpl2.0 license:asl2.0))))
|
||
|
||
(define-public nvc
|
||
(package
|
||
(name "nvc")
|
||
(version "1.16.0")
|
||
(source (origin
|
||
(method git-fetch)
|
||
(uri (git-reference
|
||
(url "https://github.com/nickg/nvc")
|
||
(commit (string-append "r" version))))
|
||
(file-name (git-file-name name version))
|
||
(sha256
|
||
(base32
|
||
"1hi1mqhjbj7r3wcdkjr6yazwpc7y9lqc0b8bj4ikfgdfsmakm3s4"))))
|
||
(build-system gnu-build-system)
|
||
(arguments
|
||
(list #:out-of-source? #t
|
||
#:configure-flags #~(list "--enable-tcl" "--enable-llvm")
|
||
#:phases #~(modify-phases %standard-phases
|
||
(add-after 'unpack 'clean-up
|
||
(lambda _
|
||
(delete-file "autogen.sh"))))))
|
||
(native-inputs
|
||
(list automake
|
||
autoconf
|
||
check ; for the tests
|
||
flex
|
||
gettext-minimal
|
||
libtool
|
||
pkg-config
|
||
python
|
||
ruby
|
||
which))
|
||
(inputs
|
||
(list libffi
|
||
llvm
|
||
readline
|
||
tcl
|
||
`(,zstd "lib")))
|
||
(synopsis "VHDL compiler and simulator")
|
||
(description "This package provides a VHDL compiler and simulator.")
|
||
(home-page "https://www.nickg.me.uk/nvc/")
|
||
(license license:gpl3+)))
|
||
|
||
(define-public systemc
|
||
(package
|
||
(name "systemc")
|
||
(version "3.0.0")
|
||
(source
|
||
(origin
|
||
(method git-fetch)
|
||
(uri (git-reference
|
||
(url "https://github.com/accellera-official/systemc")
|
||
(commit version)))
|
||
(file-name (git-file-name name version))
|
||
(sha256
|
||
(base32 "1v5fg3h9ffdzq9f6zplvr9all00ssc1gpdvbg129xahkrbl53kvw"))))
|
||
(native-inputs (list perl))
|
||
(build-system cmake-build-system)
|
||
(arguments '(#:test-target "check"))
|
||
(home-page "https://accellera.org/community/systemc")
|
||
(synopsis "Library for event-driven simulation")
|
||
(description
|
||
"SystemC is a C++ library for modeling concurrent systems, and the
|
||
reference implementation of IEEE 1666-2011. It provides a notion of timing as
|
||
well as an event-driven simulations environment. Due to its concurrent and
|
||
sequential nature, SystemC allows the description and integration of complex
|
||
hardware and software components. To some extent, SystemC can be seen as
|
||
a Hardware Description Language. However, unlike VHDL or Verilog, SystemC
|
||
provides sophisticated mechanisms that offer high abstraction levels on
|
||
components interfaces. This, in turn, facilitates the integration of systems
|
||
using different abstraction levels.")
|
||
;; homepages.cae.wisc.edu/~ece734/SystemC/Esperan_SystemC_tutorial.pdf
|
||
(license license:asl2.0)))
|
||
|
||
(define-public verilator
|
||
(package
|
||
(name "verilator")
|
||
(version "5.034")
|
||
(source
|
||
(origin
|
||
(method git-fetch)
|
||
(uri (git-reference
|
||
(url "https://github.com/verilator/verilator/")
|
||
(commit (string-append "v" version))))
|
||
(file-name (git-file-name name version))
|
||
(sha256
|
||
(base32 "14alpa2z4fqbbsyx67dz50nqcvfis8pha84545h28xmglrzm13yn"))))
|
||
(native-inputs
|
||
(list autoconf
|
||
automake
|
||
bison
|
||
flex
|
||
help2man
|
||
gettext-minimal
|
||
python
|
||
;; And a couple of extras for the test suite:
|
||
cmake-minimal
|
||
gdb/pinned
|
||
which))
|
||
(inputs
|
||
(list perl python systemc))
|
||
(build-system gnu-build-system)
|
||
(arguments
|
||
'(#:phases
|
||
(modify-phases %standard-phases
|
||
(replace 'bootstrap
|
||
(lambda _ (invoke "autoconf")))
|
||
(add-after 'unpack 'adjust-source
|
||
(lambda _
|
||
(substitute* "bin/verilator"
|
||
(("/bin/echo") "echo"))))
|
||
(add-before 'check 'disable-gdb-safe-path
|
||
(lambda _
|
||
(setenv "HOME" (getcwd))
|
||
(mkdir-p (string-append (getcwd) "/.config/gdb"))
|
||
(with-output-to-file (string-append (getcwd) "/.config/gdb/gdbinit")
|
||
(lambda ()
|
||
(display "set auto-load safe-path /"))))))
|
||
#:test-target "test"))
|
||
(home-page "https://www.veripool.org/verilator/")
|
||
(synopsis "Verilog/SystemVerilog simulator")
|
||
(description
|
||
"Verilator transforms the specified Verilog or SystemVerilog code by reading it,
|
||
performing lint checks, and optionally inserting assertion checks and
|
||
coverage-analysis points. It outputs single- or multi-threaded @file{.cpp}
|
||
and @file{.h} files.")
|
||
(license license:lgpl3)))
|
||
|
||
(define-public fftgen
|
||
(let ((commit "1d75a992efd0528edea128a903aafdabe133cb08") ;no releases
|
||
(revision "0"))
|
||
(package
|
||
(name "fftgen")
|
||
(version (git-version "0" revision commit))
|
||
(source (origin
|
||
(method git-fetch)
|
||
(uri (git-reference
|
||
(url "https://github.com/ZipCPU/dblclockfft")
|
||
(commit commit)))
|
||
(file-name (git-file-name name version))
|
||
(sha256
|
||
(base32
|
||
"0qq874yalzpjdwnxhc5df8a0ifywv29wcncb09945x56xplvkcmd"))))
|
||
(build-system gnu-build-system)
|
||
(arguments
|
||
`(#:tests? #f ;no tests
|
||
#:make-flags '("CFLAGS=-g -O2") ;default flags lack -O2
|
||
#:phases (modify-phases %standard-phases
|
||
(delete 'configure)
|
||
(replace 'install
|
||
(lambda* (#:key outputs #:allow-other-keys)
|
||
(let ((bin (string-append (assoc-ref outputs "out")
|
||
"/bin")))
|
||
(install-file "sw/fftgen" bin)))))))
|
||
(synopsis "Generic pipelined FFT core generator")
|
||
(description "fftgen produces @acronym{FFT, fast-Fourier transforms}
|
||
hardware designs in Verilog.")
|
||
(home-page "https://zipcpu.com/")
|
||
(license license:lgpl3+))))
|
||
|
||
(define-public openfpgaloader
|
||
(package
|
||
(name "openfpgaloader")
|
||
(version "0.13.1")
|
||
(source (origin
|
||
(method git-fetch)
|
||
(uri (git-reference
|
||
(url "https://github.com/trabucayre/openfpgaloader")
|
||
(commit (string-append "v" version))))
|
||
(file-name (git-file-name name version))
|
||
(sha256
|
||
(base32
|
||
"1p5qvr0bq27rp7f20ysjml7zy4bbwjx3s4yd5qjsg4b01mw4hbiq"))))
|
||
(build-system cmake-build-system)
|
||
(native-inputs
|
||
(list pkg-config))
|
||
(inputs (list eudev
|
||
hidapi
|
||
libftdi
|
||
libgpiod
|
||
libusb
|
||
zlib))
|
||
(arguments
|
||
`(#:tests? #f)) ; No tests exist
|
||
(synopsis "Utility for programming FPGA")
|
||
(description "This package provides a program to transfer a bitstream
|
||
to an FPGA.")
|
||
(home-page "https://trabucayre.github.io/openFPGALoader")
|
||
(license license:asl2.0)))
|
||
|
||
(define-public python-hdlmake
|
||
(let ((commit "9338e3e7a8784e63d16496a3fa8234d9e5aa7621")
|
||
(revision "1"))
|
||
(package
|
||
(name "python-hdlmake")
|
||
(version (git-version "3.3" revision commit))
|
||
(source
|
||
(origin
|
||
(method git-fetch)
|
||
(uri (git-reference
|
||
(url "https://gitlab.com/ohwr/project/hdl-make/")
|
||
(commit commit)))
|
||
(file-name (git-file-name name version))
|
||
(sha256
|
||
(base32 "13d0zvpch0k758r2c2vq3vhd9nbydy01jnv2ddfvb6d3xpb4wzrj"))))
|
||
(build-system pyproject-build-system)
|
||
(arguments (list #:phases #~(modify-phases %standard-phases
|
||
(add-before 'check 'chdir
|
||
(lambda _
|
||
(chdir "testsuite"))))))
|
||
(native-inputs (list python-pytest python-setuptools python-wheel))
|
||
(propagated-inputs (list python-six))
|
||
(home-page "https://gitlab.com/ohwr/project/hdl-make/")
|
||
(synopsis "Generate multi-purpose makefiles for HDL projects")
|
||
(description
|
||
"Hdlmake helps manage and share @acronym{HDL, hardware description
|
||
language} code by automatically finding file dependencies, writing synthesis
|
||
and simulation Makefiles.")
|
||
(license license:gpl3+))))
|