mirror/guile
mirror/guile
1
Fork 0
mirror of https://git.savannah.gnu.org/git/guile.git synced 2025-06-25 04:40:19 +02:00
Code Activity

ARM: Correct wrong offset for load/store of floats.

Browse source 
* lib/jit_arm-vfp.c: Correct wrong load/store offset
	calculation when the displacement is constant but too
	large to use an instruction with an immediate offset.
This commit is contained in:
pcpa 2013-10-08 01:20:19 -03:00
parent 0e94048174
commit 72f3e65a6d
2 changed files with 22 additions and 24 deletions
Download patch file Download diff file Expand all files Collapse all files

6
ChangeLog
View file

@ -1,3 +1,9 @@
2013-10-08 Paulo Andrade <pcpa@gnu.org>
* lib/jit_arm-vfp.c: Correct wrong load/store offset
calculation when the displacement is constant but too
large to use an instruction with an immediate offset.
2013-10-07 Paulo Andrade <pcpa@gnu.org>
* check/self.c: Extend tests to validate jit_callee_save_p

40
lib/jit_arm-vfp.c
View file

@ -2096,9 +2096,8 @@ _vfp_ldxi_f(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
if (jit_fpr_p(r0)) {
if (i0 >= 0) {
assert(!(i0 & 3));
i0 >>= 2;
if (i0 < 256)
VLDR_F32(r0, r1, i0);
if (i0 < 1024)
VLDR_F32(r0, r1, i0 >> 2);
else {
reg = jit_get_reg(jit_class_gpr);
addi(rn(reg), r1, i0);
@ -2109,9 +2108,8 @@ _vfp_ldxi_f(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
else {
i0 = -i0;
assert(!(i0 & 3));
i0 >>= 2;
if (i0 < 256)
VLDRN_F32(r0, r1, i0);
if (i0 < 1024)
VLDRN_F32(r0, r1, i0 >> 2);
else {
reg = jit_get_reg(jit_class_gpr);
subi(rn(reg), r1, i0);
@ -2131,9 +2129,8 @@ _vfp_ldxi_d(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
if (jit_fpr_p(r0)) {
if (i0 >= 0) {
assert(!(i0 & 3));
i0 >>= 2;
if (i0 < 256)
VLDR_F64(r0, r1, i0);
if (i0 < 1024)
VLDR_F64(r0, r1, i0 >> 2);
else {
reg = jit_get_reg(jit_class_gpr);
addi(rn(reg), r1, i0);
@ -2144,9 +2141,8 @@ _vfp_ldxi_d(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
else {
i0 = -i0;
assert(!(i0 & 3));
i0 >>= 2;
if (i0 < 256)
VLDRN_F64(r0, r1, i0);
if (i0 < 1024)
VLDRN_F64(r0, r1, i0 >> 2);
else {
reg = jit_get_reg(jit_class_gpr);
subi(rn(reg), r1, i0);
@ -2229,9 +2225,8 @@ _vfp_stxi_f(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
if (jit_fpr_p(r1)) {
if (i0 >= 0) {
assert(!(i0 & 3));
i0 >>= 2;
if (i0 < 256)
VSTR_F32(r1, r0, i0);
if (i0 < 1024)
VSTR_F32(r1, r0, i0 >> 2);
else {
reg = jit_get_reg(jit_class_gpr);
addi(rn(reg), r0, i0);
@ -2242,9 +2237,8 @@ _vfp_stxi_f(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
else {
i0 = -i0;
assert(!(i0 & 3));
i0 >>= 2;
if (i0 < 256)
VSTRN_F32(r1, r0, i0);
if (i0 < 1024)
VSTRN_F32(r1, r0, i0 >> 2);
else {
reg = jit_get_reg(jit_class_gpr);
subi(rn(reg), r0, i0);
@ -2264,9 +2258,8 @@ _vfp_stxi_d(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
if (jit_fpr_p(r1)) {
if (i0 >= 0) {
assert(!(i0 & 3));
i0 >>= 2;
if (i0 < 256)
VSTR_F64(r1, r0, i0);
if (i0 < 0124)
VSTR_F64(r1, r0, i0 >> 2);
else {
reg = jit_get_reg(jit_class_gpr);
addi(rn(reg), r0, i0);
@ -2277,9 +2270,8 @@ _vfp_stxi_d(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
else {
i0 = -i0;
assert(!(i0 & 3));
i0 >>= 2;
if (i0 < 256)
VSTRN_F64(r1, r0, i0);
if (i0 < 1024)
VSTRN_F64(r1, r0, i0 >> 2);
else {
reg = jit_get_reg(jit_class_gpr);
subi(rn(reg), r0, i0);