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riscv: movi: use addiw in RV64

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This commit is contained in:
Ekaitz Zarraga 2024-11-15 12:01:52 +01:00
parent 019cd02410
commit 746660bf08
1 changed files with 4 additions and 0 deletions
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4
lightening/riscv-cpu.c
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@ -1585,7 +1585,11 @@ movi(jit_state_t *_jit, int32_t r0, jit_word_t i0)
}
if(lo || hi == 0){
#if __WORDSIZE == 64
em_wp(_jit, _ADDIW(r0, srcreg, lo));
#elif __WORDSIZE == 32
em_wp(_jit, _ADDI(r0, srcreg, lo));
#endif
}
} else {