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Correct test cases in the mips backend.

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* lib/jit_mips-cpu.c: Correct all current test cases.
	  Call the "xori" not the "XORI" macro for jit_xori implementation,
	as the XORI macro handles only 16 bit unsigned values.
	  Call the "movr" macro, not the "movi" macro in the special
	case of adding or subtracting zero.
	  Use the proper temporary register in the jit_andr implementation.
This commit is contained in:
pcpa 2012-12-10 21:14:50 -02:00
parent e255b76068
commit a3fbc5da96
2 changed files with 13 additions and 4 deletions
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9
ChangeLog
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@ -1,3 +1,12 @@
2012-12-10 Paulo Andrade <pcpa@gnu.org>
* lib/jit_mips-cpu.c: Correct all current test cases.
Call the "xori" not the "XORI" macro for jit_xori implementation,
as the XORI macro handles only 16 bit unsigned values.
Call the "movr" macro, not the "movi" macro in the special
case of adding or subtracting zero.
Use the proper temporary register in the jit_andr implementation.
2012-12-09 Paulo Andrade <pcpa@gnu.org>
* check/alu.inc, check/alu_add.ok, check/alu_add.tst,

8
lib/jit_mips-cpu.c
View file

@ -364,7 +364,7 @@ static void _nop(jit_state_t*,jit_int32_t);
# define JR(r0) hrrrit(MIPS_SPECIAL,r0,0,0,0,MIPS_JR)
# define J(i0) hi(MIPS_J, i0)
# define MOVZ(rd,rs,rt) hrrrit(0,rs,rt,rd,0,MIPS_MOVZ)
# define comr(r0,r1) XORI(r0, r1, -1)
# define comr(r0,r1) xori(r0, r1, -1)
# define negr(r0,r1) SUBU(r0,_ZERO_REGNO,r1)
# define addr(rd,rs,rt) ADDU(rd,rs,rt)
# define addi(r0,r1,i0) _addi(_jit,r0,r1,i0)
@ -715,7 +715,7 @@ _addi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
{
jit_int32_t reg;
if (i0 == 0)
movi(r0, r1);
movr(r0, r1);
else if (can_sign_extend_short_p(i0))
ADDIU(r0, r1, i0);
else {
@ -807,7 +807,7 @@ _subi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
{
jit_int32_t reg;
if (i0 == 0)
movi(r0, r1);
movr(r0, r1);
else if (can_sign_extend_short_p(i0) && (i0 & 0xffff) != 0x8000)
ADDIU(r0, r1, -i0);
else {
@ -2644,7 +2644,7 @@ _bmcr(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
jit_word_t w;
jit_int32_t t0;
t0 = jit_get_reg(jit_class_gpr);
AND(rn(r0), r0, r1);
AND(rn(t0), r0, r1);
w = _jit->pc.w;
BEQ(_ZERO_REGNO, rn(t0), ((i0 - w) >> 2) - 1);
NOP(1);