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guile/module/system
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Shea Levy d6e669b8cb
Recognize RISC-V compilation targets. 
* module/system/base/target.scm (cpu-endianness): Add case for "riscv" variants.

Signed-off-by: Shea Levy <shea@shealevy.com>
Signed-off-by: Mark H Weaver <mhw@netris.org>
2018-03-15 23:17:23 -04:00
..
base Recognize RISC-V compilation targets. 2018-03-15 23:17:23 -04:00
repl REPL Server: Guard against HTTP inter-protocol exploitation attacks. 2016-10-11 11:29:09 +02:00
vm Fix trap handlers to handle applicable structs. 2014-01-09 03:12:05 +00:00
foreign.scm Improve correctness and consistency of 'eval-when' usage. 2014-01-23 10:41:22 -05:00
xref.scm system xref maintains source mapping for nested procedures too 2010-09-24 13:24:48 +02:00