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guile/module/system/base
Shea Levy d6e669b8cb
Recognize RISC-V compilation targets.
* module/system/base/target.scm (cpu-endianness): Add case for "riscv" variants.

Signed-off-by: Shea Levy <shea@shealevy.com>
Signed-off-by: Mark H Weaver <mhw@netris.org>
2018-03-15 23:17:23 -04:00
..
ck.scm Improve error for set-fields paths leading to different types. 2012-11-10 01:37:20 -05:00
compile.scm Allow mkstemp! to have optional "mode" argument 2016-07-16 15:37:55 +02:00
lalr.scm add source-location->source-properties to lalr 2010-11-18 12:31:28 +01:00
lalr.upstream.scm Update (system base lalr) from upstream. 2014-12-02 21:25:56 +01:00
language.scm Add 'for-humans?' flag to <language> specifications. 2013-01-27 10:16:40 -05:00
message.scm Fix typo in comment in message.scm: 'know' to 'known' warning types 2012-02-14 23:39:22 -05:00
pmatch.scm pmatch: always wrap with let, even if the expression appears atomic 2012-03-01 16:16:27 -05:00
syntax.scm psyntax: Generate identifiers in a deterministic fashion. 2016-12-30 21:58:44 +01:00
target.scm Recognize RISC-V compilation targets. 2018-03-15 23:17:23 -04:00
types.scm Handle zero-length bytevectors correctly in (system base types). 2015-03-26 23:18:39 -04:00