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Pass all but the (not yet implemented) qmul and qdiv tests in sparc
* check/float.tst: Add sparc to list of known NaN and +-Inf to integer conversion. * check/lightning.c: Define __sparc__ to preprocessor in the sparc backend. * include/lightning/jit_private.h: Correct wrong definition of emit_stxi_d, that has lived for a long time, but would cause problems whenever needing to spill/reload a float register. * include/lightning/jit_sparc.h: Can only use %g2,%g3,%g4 for scratch variables, as other "global" registers are reserved for the system, e.g. libc. Reorder float register naming to make it easier to access odd float registers, so that generating code for pusharg and getarg is easier for the IR. * lib/jit_mips-cpu.c, lib/jit_ppc-cpu.c: Update to match new code in jit_sparc-cpu.c. It must call jit_get_reg with jit_class_nospill if using the register to move an unconditional branch address to it, as the reload will not happen (actually could happen in the delay slot...) * lib/jit_sparc-cpu.c: Correct wrong macro definition for ldxr_s. Properly implement div* and implement rem. Div* needs to use the y register, and rem* needs to be synthesized. Correct b?sub* macro definitions. * lib/jit_sparc-fpu.c: Correct reversed float to/from double conversion. Correct wrong jit_get_reg call asking for a gpr and then using the fpr with that number. Correct wrong branch displacement computation for conditional branches. * lib/jit_sparc.c: Correct getarg_d and pushargi_d implementation. Add rem* entries to the switch converting IR to machine code. * lib/lightning.c: Correct a problem detected when adding the jit_class_nospill flag to jit_get_reg, that was caused when having a branch to an "epilog" node, what would cause the code to think all registers in unknown state were live, while in truth, all registers in unknown state in the "just after return" point are actually dead.
This commit is contained in:
pcpa
parent
610a569300
commit
e304bc8bf9
11 changed files with 238 additions and 81 deletions
50
ChangeLog
50
ChangeLog
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@ -1,3 +1,53 @@
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2013-02-18 Paulo Andrade <pcpa@gnu.org>
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* check/float.tst: Add sparc to list of known NaN and +-Inf
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to integer conversion.
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* check/lightning.c: Define __sparc__ to preprocessor in
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the sparc backend.
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* include/lightning/jit_private.h: Correct wrong definition
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of emit_stxi_d, that has lived for a long time, but would
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cause problems whenever needing to spill/reload a float
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register.
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* include/lightning/jit_sparc.h: Can only use %g2,%g3,%g4
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for scratch variables, as other "global" registers are
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reserved for the system, e.g. libc.
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Reorder float register naming to make it easier to
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access odd float registers, so that generating code for
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pusharg and getarg is easier for the IR.
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* lib/jit_mips-cpu.c, lib/jit_ppc-cpu.c: Update to match
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new code in jit_sparc-cpu.c. It must call jit_get_reg
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with jit_class_nospill if using the register to move
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an unconditional branch address to it, as the reload
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will not happen (actually could happen in the delay
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slot...)
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* lib/jit_sparc-cpu.c: Correct wrong macro definition for
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ldxr_s.
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Properly implement div* and implement rem. Div* needs
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to use the y register, and rem* needs to be synthesized.
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Correct b?sub* macro definitions.
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* lib/jit_sparc-fpu.c: Correct reversed float to/from double
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conversion.
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Correct wrong jit_get_reg call asking for a gpr and then
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using the fpr with that number.
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Correct wrong branch displacement computation for
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conditional branches.
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* lib/jit_sparc.c: Correct getarg_d and pushargi_d implementation.
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Add rem* entries to the switch converting IR to machine code.
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* lib/lightning.c: Correct a problem detected when adding
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the jit_class_nospill flag to jit_get_reg, that was caused
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when having a branch to an "epilog" node, what would cause
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the code to think all registers in unknown state were live,
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while in truth, all registers in unknown state in the
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"just after return" point are actually dead.
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2013-02-17 Paulo Andrade <pcpa@gnu.org>
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* include/lightning/jit_sparc.h, lib/jit_sparc-cpu.c,
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@ -14,14 +14,14 @@ ok:
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# define x80 0x8000000000000000
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#endif
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#if __mips__
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#if __mips__ || __sparc__
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# define wnan x7f
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#elif __arm__
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# define wnan 0
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#else
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# define wnan x80
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#endif
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#if __mips__ || __arm__ || __ppc__
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#if __mips__ || __arm__ || __ppc__ || __sparc__
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# define wpinf x7f
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#else
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# define wpinf x80
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@ -3962,6 +3962,11 @@ main(int argc, char *argv[])
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opt_short += snprintf(cmdline + opt_short,
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sizeof(cmdline) - opt_short,
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" -D__arm__=1");
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#endif
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#if defined(__sparc__)
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opt_short += snprintf(cmdline + opt_short,
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sizeof(cmdline) - opt_short,
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" -D__sparc__=1");
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#endif
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if ((parser.fp = popen(cmdline, "r")) == NULL)
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error("cannot execute %s", cmdline);
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@ -440,7 +440,7 @@ _emit_stxi(jit_state_t*, jit_word_t, jit_int32_t, jit_int32_t);
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extern void
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_emit_ldxi_d(jit_state_t*, jit_int32_t, jit_int32_t, jit_word_t);
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#define emit_stxi_d(i0, r0, r1) _emit_stxi(_jit, i0, r0, r1)
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#define emit_stxi_d(i0, r0, r1) _emit_stxi_d(_jit, i0, r0, r1)
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extern void
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_emit_stxi_d(jit_state_t*, jit_word_t, jit_int32_t, jit_int32_t);
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@ -28,11 +28,11 @@
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typedef enum {
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#define jit_arg_reg_p(i) ((i) >= 0 && (i) < 6)
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#define jit_r(i) (_G2 + (i))
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#define jit_r_num() 6
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#define jit_r_num() 3
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#define jit_v(i) (_L0 + (i))
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#define jit_v_num() 8
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#define jit_arg_f_reg_p(i) ((i) >= 0 && (i) < 6)
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#define jit_f(i) (_F0 + (i))
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#define jit_f(i) (_F0 + ((i) << 1))
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#define jit_f_num() 8
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#define JIT_R0 _G2
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#define JIT_R1 _G3
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@ -45,12 +45,13 @@ typedef enum {
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_L0, _L1, _L2, _L3, _L4, _L5, _L6, _L7,
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_I0, _I1, _I2, _I3, _I4, _I5, _FP, _I7,
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#define JIT_F0 _F0
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#define JIT_F1 _F1
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#define JIT_F2 _F2
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#define JIT_F3 _F3
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#define JIT_F4 _F4
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#define JIT_F5 _F5
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#define JIT_F1 _F2
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#define JIT_F2 _F4
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#define JIT_F3 _F6
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#define JIT_F4 _F8
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#define JIT_F5 _F10
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_F0, _F1, _F2, _F3, _F4, _F5, _F6, _F7,
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_F8, _F9, _F10, _F11, _F12, _F13, _F14, _F15,
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#define JIT_NOREG _NOREG
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_NOREG,
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} jit_reg_t;
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@ -2223,7 +2223,7 @@ _jmpi(jit_state_t *_jit, jit_word_t i0)
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NOP(1);
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}
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else {
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reg = jit_get_reg(jit_class_gpr);
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reg = jit_get_reg(jit_class_gpr|jit_class_nospill);
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movi_p(rn(reg), i0);
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jmpr(rn(reg));
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jit_unget_reg(reg);
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@ -2410,7 +2410,7 @@ _jmpi(jit_state_t *_jit, jit_word_t i0)
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{
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jit_int32_t reg;
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jit_word_t w, d;
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reg = jit_get_reg(jit_class_gpr);
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reg = jit_get_reg(jit_class_gpr|jit_class_nospill);
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w = _jit->pc.w;
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d = (i0 - w) & ~3;
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B(d);
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@ -2424,7 +2424,7 @@ _jmpi_p(jit_state_t *_jit, jit_word_t i0)
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{
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jit_word_t w;
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jit_int32_t reg;
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reg = jit_get_reg(jit_class_gpr);
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reg = jit_get_reg(jit_class_gpr|jit_class_nospill);
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w = movi_p(rn(reg), i0);
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jmpr(rn(reg));
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jit_unget_reg(reg);
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@ -93,7 +93,7 @@ static void _f3a(jit_state_t*,jit_int32_t,
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# define LDSB(rs1, rs2, rd) f3r(3, rd, 9, rs1, rs2)
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# define LDSBI(rs1, imm, rd) f3i(3, rd, 9, rs1, imm)
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# define LDSH(rs1, rs2, rd) f3r(3, rd, 10, rs1, rs2)
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# define LDSHI(rs1, imm, rd) f3r(3, rd, 10, rs1, imm)
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# define LDSHI(rs1, imm, rd) f3i(3, rd, 10, rs1, imm)
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# define LDUB(rs1, rs2, rd) f3r(3, rd, 1, rs1, rs2)
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# define LDUBI(rs1, imm, rd) f3i(3, rd, 1, rs1, imm)
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# define LDUH(rs1, rs2, rd) f3r(3, rd, 2, rs1, rs2)
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@ -461,12 +461,22 @@ static void _subxi(jit_state_t*, jit_int32_t, jit_int32_t, jit_word_t);
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# define muli(r0, r1, i0) _muli(_jit, r0, r1, i0)
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static void _muli(jit_state_t*, jit_int32_t, jit_int32_t, jit_word_t);
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# define divr(r0, r1, r2) SDIV(r1, r2, r0)
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# define divr(r0, r1, r2) _divr(_jit, r0, r1, r2)
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static void _divr(jit_state_t*, jit_int32_t, jit_int32_t, jit_int32_t);
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# define divi(r0, r1, i0) _divi(_jit, r0, r1, i0)
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static void _divi(jit_state_t*, jit_int32_t, jit_int32_t, jit_word_t);
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# define divr_u(r0, r1, r2) UDIV(r1, r2, r0)
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# define divr_u(r0, r1, r2) _divr_u(_jit, r0, r1, r2)
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static void _divr_u(jit_state_t*, jit_int32_t, jit_int32_t, jit_int32_t);
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# define divi_u(r0, r1, i0) _divi_u(_jit, r0, r1, i0)
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static void _divi_u(jit_state_t*, jit_int32_t, jit_int32_t, jit_word_t);
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# define remr(r0, r1, r2) _remr(_jit, r0, r1, r2)
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static void _remr(jit_state_t*, jit_int32_t, jit_int32_t, jit_int32_t);
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# define remi(r0, r1, i0) _remi(_jit, r0, r1, i0)
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static void _remi(jit_state_t*, jit_int32_t, jit_int32_t, jit_word_t);
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# define remr_u(r0, r1, r2) _remr_u(_jit, r0, r1, r2)
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static void _remr_u(jit_state_t*, jit_int32_t, jit_int32_t, jit_int32_t);
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# define remi_u(r0, r1, i0) _remi_u(_jit, r0, r1, i0)
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static void _remi_u(jit_state_t*, jit_int32_t, jit_int32_t, jit_word_t);
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# define andr(r0, r1, r2) AND(r1, r2, r0)
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# define andi(r0, r1, i0) _andi(_jit, r0, r1, i0)
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@ -619,14 +629,14 @@ _b_asw(jit_state_t*,jit_bool_t,jit_bool_t,jit_bool_t,
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# define bxaddi(i0, r0, i1) b_asw(0, 1, 1, i0, r0, i1)
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# define bxaddr_u(i0, r0, r1) b_asr(0, 1, 0, i0, r0, r1)
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# define bxaddi_u(i0, r0, i1) b_asw(0, 1, 0, i0, r0, i1)
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# define bosubr(i0, r0, r1) b_asr(1, 1, 1, i0, r0, r1)
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# define bosubi(i0, r0, i1) b_asw(1, 1, 1, i0, r0, i1)
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# define bosubr_u(i0, r0, r1) b_asr(1, 1, 0, i0, r0, r1)
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# define bosubi_u(i0, r0, i1) b_asw(1, 1, 0, i0, r0, i1)
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# define bxsubr(i0, r0, r1) b_asr(0, 1, 1, i0, r0, r1)
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# define bxsubi(i0, r0, i1) b_asw(0, 1, 1, i0, r0, i1)
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# define bxsubr_u(i0, r0, r1) b_asr(0, 1, 0, i0, r0, r1)
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# define bxsubi_u(i0, r0, i1) b_asw(0, 1, 0, i0, r0, i1)
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# define bosubr(i0, r0, r1) b_asr(1, 0, 1, i0, r0, r1)
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# define bosubi(i0, r0, i1) b_asw(1, 0, 1, i0, r0, i1)
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# define bosubr_u(i0, r0, r1) b_asr(1, 0, 0, i0, r0, r1)
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# define bosubi_u(i0, r0, i1) b_asw(1, 0, 0, i0, r0, i1)
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# define bxsubr(i0, r0, r1) b_asr(0, 0, 1, i0, r0, r1)
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# define bxsubi(i0, r0, i1) b_asw(0, 0, 1, i0, r0, i1)
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# define bxsubr_u(i0, r0, r1) b_asr(0, 0, 0, i0, r0, r1)
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# define bxsubi_u(i0, r0, i1) b_asw(0, 0, 0, i0, r0, i1)
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# define bm_r(set, i0, r0, r1) _bm_r(_jit,set,i0,r0,r1)
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static jit_word_t
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_bm_r(jit_state_t*,jit_bool_t,jit_word_t,jit_int32_t,jit_int32_t);
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@ -925,26 +935,49 @@ _muli(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
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}
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}
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static void
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_divr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
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{
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jit_int32_t reg;
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reg = jit_get_reg(jit_class_gpr);
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rshi(rn(reg), r1, 31);
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WRY(rn(reg), 0);
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SDIV(r1, r2, r0);
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jit_unget_reg(reg);
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}
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static void
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_divi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
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{
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jit_int32_t reg;
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if (s13_p(i0))
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SDIVI(r1, i0, r0);
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else {
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reg = jit_get_reg(jit_class_gpr);
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if (s13_p(i0)) {
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rshi(rn(reg), r1, 31);
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WRY(rn(reg), 0);
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SDIVI(r1, i0, r0);
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}
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else {
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movi(rn(reg), i0);
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divr(r0, r1, rn(reg));
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}
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jit_unget_reg(reg);
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}
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static void
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_divr_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
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{
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WRYI(0, 0);
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UDIV(r1, r2, r0);
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}
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static void
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_divi_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
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{
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jit_int32_t reg;
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if (s13_p(i0))
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if (s13_p(i0)) {
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WRYI(0, 0);
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UDIVI(r1, i0, r0);
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}
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else {
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reg = jit_get_reg(jit_class_gpr);
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movi(rn(reg), i0);
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@ -953,6 +986,62 @@ _divi_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
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}
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}
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static void
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_remr(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
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{
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jit_int32_t reg;
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if (r0 == r1 || r0 == r2) {
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reg = jit_get_reg(jit_class_gpr);
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divr(rn(reg), r1, r2);
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mulr(rn(reg), r2, rn(reg));
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subr(r0, r1, rn(reg));
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jit_unget_reg(reg);
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}
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else {
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divr(r0, r1, r2);
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mulr(r0, r2, r0);
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subr(r0, r1, r0);
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}
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}
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static void
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_remi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
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{
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jit_int32_t reg;
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reg = jit_get_reg(jit_class_gpr);
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movi(rn(reg), i0);
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remr(r0, r1, rn(reg));
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jit_unget_reg(reg);
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}
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static void
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_remr_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_int32_t r2)
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{
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jit_int32_t reg;
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if (r0 == r1 || r0 == r2) {
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reg = jit_get_reg(jit_class_gpr);
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divr_u(rn(reg), r1, r2);
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||||
mulr(rn(reg), r2, rn(reg));
|
||||
subr(r0, r1, rn(reg));
|
||||
jit_unget_reg(reg);
|
||||
}
|
||||
else {
|
||||
divr_u(r0, r1, r2);
|
||||
mulr(r0, r2, r0);
|
||||
subr(r0, r1, r0);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
_remi_u(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
|
||||
{
|
||||
jit_int32_t reg;
|
||||
reg = jit_get_reg(jit_class_gpr);
|
||||
movi(rn(reg), i0);
|
||||
remr_u(r0, r1, rn(reg));
|
||||
jit_unget_reg(reg);
|
||||
}
|
||||
|
||||
static void
|
||||
_andi(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1, jit_word_t i0)
|
||||
{
|
||||
|
|
@ -1316,6 +1405,7 @@ _b_asr(jit_state_t *_jit, jit_bool_t jif, jit_bool_t add, jit_bool_t sgn,
|
|||
(jif ? SPARC_BVS : SPARC_BVC) :
|
||||
(jif ? SPARC_BCS : SPARC_BCC),
|
||||
(i0 - w) >> 2);
|
||||
NOP();
|
||||
return (w);
|
||||
}
|
||||
|
||||
|
|
@ -1327,14 +1417,15 @@ _b_asw(jit_state_t *_jit, jit_bool_t jif, jit_bool_t add, jit_bool_t sgn,
|
|||
jit_int32_t reg;
|
||||
if (s13_p(i1)) {
|
||||
if (add)
|
||||
ADDcc(r0, i1, r0);
|
||||
ADDIcc(r0, i1, r0);
|
||||
else
|
||||
SUBcc(r0, i1, r0);
|
||||
SUBIcc(r0, i1, r0);
|
||||
w = _jit->pc.w;
|
||||
B(sgn ?
|
||||
(jif ? SPARC_BVS : SPARC_BVC) :
|
||||
(jif ? SPARC_BCS : SPARC_BCC),
|
||||
(i0 - w) >> 2);
|
||||
NOP();
|
||||
}
|
||||
else {
|
||||
reg = jit_get_reg(jit_class_gpr);
|
||||
|
|
@ -1396,9 +1487,10 @@ _jmpi(jit_state_t *_jit, jit_word_t i0)
|
|||
NOP();
|
||||
}
|
||||
else {
|
||||
reg = jit_get_reg(jit_class_gpr);
|
||||
reg = jit_get_reg(jit_class_gpr|jit_class_nospill);
|
||||
movi(rn(reg), i0);
|
||||
jmpr(rn(reg));
|
||||
jit_unget_reg(reg);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1407,7 +1499,7 @@ _jmpi_p(jit_state_t *_jit, jit_word_t i0)
|
|||
{
|
||||
jit_word_t w;
|
||||
jit_int32_t reg;
|
||||
reg = jit_get_reg(jit_class_gpr);
|
||||
reg = jit_get_reg(jit_class_gpr|jit_class_nospill);
|
||||
w = movi_p(rn(reg), i0);
|
||||
jmpr(rn(reg));
|
||||
jit_unget_reg(reg);
|
||||
|
|
@ -1446,8 +1538,9 @@ static void
|
|||
_prolog(jit_state_t *_jit, jit_node_t *node)
|
||||
{
|
||||
/* align at 16 bytes boundary */
|
||||
_jit->function->stack = ((stack_framesize - _jit->function->self.aoff)
|
||||
+ 15) & -16;
|
||||
_jit->function->stack = ((stack_framesize +
|
||||
_jit->function->self.alen -
|
||||
_jit->function->self.aoff) + 15) & -16;
|
||||
SAVEI(_SP_REGNO, -_jit->function->stack, _SP_REGNO);
|
||||
|
||||
/* (most) other backends do not save incoming arguments, so,
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@
|
|||
# define SPARC_FBG 6 /* greater - G */
|
||||
# define SPARC_FBUG 5 /* unordered or greater - G or U */
|
||||
# define SPARC_FBL 4 /* less - L */
|
||||
# define SPARC_FBUL 5 /* unordered or less - L or U */
|
||||
# define SPARC_FBUL 3 /* unordered or less - L or U */
|
||||
# define SPARC_FBLG 2 /* less or greater - L or G */
|
||||
# define SPARC_FBNE 1 /* not equal - L or G or U */
|
||||
# define SPARC_FBNZ SPARC_FBNE
|
||||
|
|
@ -147,7 +147,7 @@ static void _extr_f(jit_state_t*, jit_int32_t, jit_int32_t);
|
|||
# define truncr_f(r0, r1) truncr_f_i(r0, r1)
|
||||
# define truncr_f_i(r0, r1) _truncr_f_i(_jit, r0, r1)
|
||||
static void _truncr_f_i(jit_state_t*, jit_int32_t, jit_int32_t);
|
||||
# define extr_d_f(r0, r1) FSTOD(r1, r0)
|
||||
# define extr_d_f(r0, r1) FDTOS(r1, r0)
|
||||
# define movi_f(r0, i0) ldi_f(r0, (jit_word_t)i0)
|
||||
# define movr_f(r0, r1) FMOVS(r1, r0)
|
||||
# define negr_f(r0, r1) FNEGS(r1, r0)
|
||||
|
|
@ -159,7 +159,7 @@ static void _extr_d(jit_state_t*, jit_int32_t, jit_int32_t);
|
|||
# define truncr_d(r0, r1) truncr_d_i(r0, r1)
|
||||
# define truncr_d_i(r0, r1) _truncr_d_i(_jit, r0, r1)
|
||||
static void _truncr_d_i(jit_state_t*, jit_int32_t, jit_int32_t);
|
||||
# define extr_f_d(r0, r1) FDTOS(r1, r0)
|
||||
# define extr_f_d(r0, r1) FSTOD(r1, r0)
|
||||
# define movi_d(r0, i0) ldi_d(r0, (jit_word_t)i0)
|
||||
# define movr_d(r0, r1) _movr_d(_jit, r0, r1)
|
||||
static void _movr_d(jit_state_t*, jit_int32_t, jit_int32_t);
|
||||
|
|
@ -415,7 +415,7 @@ _fop1f(jit_state_t *_jit, jit_int32_t op,
|
|||
jit_int32_t r0, jit_int32_t r1, jit_float32_t *i0)
|
||||
{
|
||||
jit_int32_t reg;
|
||||
reg = jit_get_reg(jit_class_gpr);
|
||||
reg = jit_get_reg(jit_class_fpr);
|
||||
movi_f(rn(reg), i0);
|
||||
FPop1(r0, r1, op, rn(reg));
|
||||
jit_unget_reg(reg);
|
||||
|
|
@ -426,7 +426,7 @@ _fop1d(jit_state_t *_jit, jit_int32_t op,
|
|||
jit_int32_t r0, jit_int32_t r1, jit_float64_t *i0)
|
||||
{
|
||||
jit_int32_t reg;
|
||||
reg = jit_get_reg(jit_class_gpr);
|
||||
reg = jit_get_reg(jit_class_fpr);
|
||||
movi_d(rn(reg), i0);
|
||||
FPop1(r0, r1, op, rn(reg));
|
||||
jit_unget_reg(reg);
|
||||
|
|
@ -444,7 +444,7 @@ static void
|
|||
_truncr_f_i(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
|
||||
{
|
||||
jit_int32_t reg;
|
||||
reg = jit_get_reg(jit_class_gpr);
|
||||
reg = jit_get_reg(jit_class_fpr);
|
||||
FSTOI(r1, rn(reg));
|
||||
stxi_f(-8, _FP_REGNO, rn(reg));
|
||||
ldxi_i(r0, _FP_REGNO, -8);
|
||||
|
|
@ -558,8 +558,8 @@ _stxi_f(jit_state_t *_jit, jit_word_t i0, jit_int32_t r0, jit_int32_t r1)
|
|||
static void
|
||||
_extr_d(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
|
||||
{
|
||||
stxi(-4, _FP_REGNO, r1);
|
||||
stxi(-8, _FP_REGNO, 0);
|
||||
stxi(-8, _FP_REGNO, r1);
|
||||
stxi(-4, _FP_REGNO, 0);
|
||||
ldxi_d(r0, _FP_REGNO, -8);
|
||||
FITOD(r0, r0);
|
||||
}
|
||||
|
|
@ -568,10 +568,10 @@ static void
|
|||
_truncr_d_i(jit_state_t *_jit, jit_int32_t r0, jit_int32_t r1)
|
||||
{
|
||||
jit_int32_t reg;
|
||||
reg = jit_get_reg(jit_class_gpr);
|
||||
reg = jit_get_reg(jit_class_fpr);
|
||||
FDTOI(r1, rn(reg));
|
||||
stxi_d(-8, _FP_REGNO, rn(reg));
|
||||
ldxi_i(r0, _FP_REGNO, -4);
|
||||
ldxi_i(r0, _FP_REGNO, -8);
|
||||
jit_unget_reg(reg);
|
||||
}
|
||||
|
||||
|
|
@ -638,7 +638,7 @@ _fbr(jit_state_t *_jit, jit_int32_t cc,
|
|||
jit_word_t w;
|
||||
FCMPS(r0, r1);
|
||||
w = _jit->pc.w;
|
||||
FB(cc, ((i0 - w) >> 2) - 1);
|
||||
FB(cc, (i0 - w) >> 2);
|
||||
NOP();
|
||||
return (w);
|
||||
}
|
||||
|
|
@ -654,7 +654,7 @@ _fbw(jit_state_t *_jit, jit_int32_t cc,
|
|||
FCMPS(r0, rn(reg));
|
||||
jit_unget_reg(reg);
|
||||
w = _jit->pc.w;
|
||||
FB(cc, ((i0 - w) >> 2) - 1);
|
||||
FB(cc, (i0 - w) >> 2);
|
||||
NOP();
|
||||
return (w);
|
||||
}
|
||||
|
|
@ -666,7 +666,7 @@ _dbr(jit_state_t *_jit, jit_int32_t cc,
|
|||
jit_word_t w;
|
||||
FCMPD(r0, r1);
|
||||
w = _jit->pc.w;
|
||||
FB(cc, ((i0 - w) >> 2) - 1);
|
||||
FB(cc, (i0 - w) >> 2);
|
||||
NOP();
|
||||
return (w);
|
||||
}
|
||||
|
|
@ -682,7 +682,7 @@ _dbw(jit_state_t *_jit, jit_int32_t cc,
|
|||
FCMPD(r0, rn(reg));
|
||||
jit_unget_reg(reg);
|
||||
w = _jit->pc.w;
|
||||
FB(cc, ((i0 - w) >> 2) - 1);
|
||||
FB(cc, (i0 - w) >> 2);
|
||||
NOP();
|
||||
return (w);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -39,9 +39,9 @@ jit_register_t _rvs[] = {
|
|||
{ rc(gpr) | 0x02, "%g2" },
|
||||
{ rc(gpr) | 0x03, "%g3" },
|
||||
{ rc(gpr) | 0x04, "%g4" },
|
||||
{ rc(gpr) | 0x05, "%g5" },
|
||||
{ rc(gpr) | 0x06, "%g6" },
|
||||
{ rc(gpr) | 0x07, "%g7" },
|
||||
{ 0x05, "%g5" },
|
||||
{ 0x06, "%g6" },
|
||||
{ 0x07, "%g7" },
|
||||
{ rc(arg) | rc(gpr) | 0x08, "%o0" },
|
||||
{ rc(arg) | rc(gpr) | 0x09, "%o1" },
|
||||
{ rc(arg) | rc(gpr) | 0x0a, "%o2" },
|
||||
|
|
@ -67,13 +67,21 @@ jit_register_t _rvs[] = {
|
|||
{ rc(sav) | 0x1e, "%fp" },
|
||||
{ 0x1f, "%i7" },
|
||||
{ rc(fpr) | 0x00, "%f0" },
|
||||
{ 0x01, "%f1" },
|
||||
{ rc(fpr) | 0x02, "%f2" },
|
||||
{ 0x03, "%f3" },
|
||||
{ rc(fpr) | 0x04, "%f4" },
|
||||
{ 0x05, "%f5" },
|
||||
{ rc(fpr) | 0x06, "%f6" },
|
||||
{ 0x06, "%f7" },
|
||||
{ rc(fpr) | 0x08, "%f8" },
|
||||
{ 0x09, "%f9" },
|
||||
{ rc(fpr) | 0x0a, "%f10" },
|
||||
{ 0x0b, "%f11" },
|
||||
{ rc(fpr) | 0x0c, "%f12" },
|
||||
{ 0x0d, "%f13" },
|
||||
{ rc(fpr) | 0x0e, "%f14" },
|
||||
{ 0x0f, "%f15" },
|
||||
{ _NOREG, "<none>" },
|
||||
};
|
||||
|
||||
|
|
@ -364,12 +372,10 @@ _jit_getarg_d(jit_state_t *_jit, jit_int32_t u, jit_node_t *v)
|
|||
else if (v->u.w < 6) {
|
||||
jit_stxi(-8, JIT_FP, _I0 + v->u.w);
|
||||
jit_ldxi_f(u, JIT_FP, -8);
|
||||
jit_ldxi_f(u, JIT_FP, stack_framesize);
|
||||
}
|
||||
else {
|
||||
jit_ldxi_f(u, JIT_FP, v->u.w);
|
||||
jit_ldxi_f(u + 1, JIT_FP, v->u.w + 4);
|
||||
jit_ldxi_f(u + 1, JIT_FP, stack_framesize);
|
||||
}
|
||||
else
|
||||
jit_ldxi_d(u, JIT_FP, v->u.w);
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -469,7 +475,7 @@ _jit_pushargi_d(jit_state_t *_jit, jit_float64_t u)
|
|||
_jit->function->call.argi += 2;
|
||||
}
|
||||
else if (_jit->function->call.argi < 6) {
|
||||
jit_stxi_d(-8, JIT_FP, regno);
|
||||
jit_stxi_f(-8, JIT_FP, regno);
|
||||
jit_ldxi(_O0 + _jit->function->call.argi, JIT_FP, -8);
|
||||
++_jit->function->call.argi;
|
||||
jit_stxi_f(stack_framesize, JIT_SP, regno + 1);
|
||||
|
|
@ -713,6 +719,10 @@ _emit_code(jit_state_t *_jit)
|
|||
case_rrw(div,);
|
||||
case_rrr(div, _u);
|
||||
case_rrw(div, _u);
|
||||
case_rrr(rem,);
|
||||
case_rrw(rem,);
|
||||
case_rrr(rem, _u);
|
||||
case_rrw(rem, _u);
|
||||
|
||||
case_rrr(and,);
|
||||
case_rrw(and,);
|
||||
|
|
|
|||
|
|
@ -1636,7 +1636,6 @@ _jit_update(jit_state_t *_jit, jit_node_t *node,
|
|||
node = label;
|
||||
goto restart;
|
||||
}
|
||||
if (label->code == jit_code_label) {
|
||||
block = _jit->blocks.ptr + label->v.w;
|
||||
if (mpz_tstbit(_jit->blockmask, label->v.w))
|
||||
continue;
|
||||
|
|
@ -1661,7 +1660,6 @@ _jit_update(jit_state_t *_jit, jit_node_t *node,
|
|||
}
|
||||
continue;
|
||||
}
|
||||
}
|
||||
/* assume value is live due to jump to unknown location */
|
||||
jit_regset_ior(*live, *live, *mask);
|
||||
jit_regset_set_ui(*mask, 0);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue